參數(shù)資料
型號(hào): 73S8024RN-32IMR
廠商: TERIDIAN SEMICONDUCTOR CORP
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, QCC32
封裝: QFN-32
文件頁(yè)數(shù): 21/23頁(yè)
文件大?。?/td> 318K
代理商: 73S8024RN-32IMR
73S8024RN
Low Cost Smart Card Interface
DATA SHEET
Page: 7 of 23
2005 TERIDIAN Semiconductor Corporation
Rev 1.5
ACTIVATION SEQUENCE
The TERIDIAN 73S8024RN smart card interface IC has an internal 10ms delay at power on reset or on the
application of VDD > VDDF. No activation is allowed at this time. The CMDVCC (edge triggered) must then be set
low to activate the card. In order to initiate activation, the card must be present; there can be no over-
temperature fault or no VDD fault.
The following steps show the activation sequence and the timing of the card control signals when the system
controller sets
CMDVCC low while the RSTIN is low:
-
CMDVCC is set low.
-
Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation,
the voltage VCC to the card becomes valid during t1. If VCC does not become valid, the OFF goes low
to report a fault to the system controller, and the power VCC to the card is shut off.
-
Turn I/O (AUX1, AUX2) to reception mode at the end of (t2).
-
CLK is applied to the card at the end of (t3).
-
RST is a copy of RSTIN after (t4). RSTIN may be set high before t4, however the sequencer won’t set
RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
I/O
CLK
RSTIN
t
1
t
2
t
3
t
4
RST
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5s, I/O goes to reception state
t3 = >0.5s, CLK starts
t4 42000 card clock cycles. Time for RST to become the copy of RSTIN
Figure 2: Activation Sequence – RSTIN low when
CMDVCC goes low
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相關(guān)代理商/技術(shù)參數(shù)
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