參數(shù)資料
型號(hào): 73S8024RN-32IM
廠商: TERIDIAN SEMICONDUCTOR CORP
元件分類(lèi): 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, QCC32
封裝: QFN-32
文件頁(yè)數(shù): 23/23頁(yè)
文件大小: 318K
代理商: 73S8024RN-32IM
73S8024RN
Low Cost Smart Card Interface
DATA SHEET
Page: 9 of 23
2005 TERIDIAN Semiconductor Corporation
Rev 1.5
DEACTIVATION SEQUENCE
Deactivation is initiated either by the system controller by setting the
CMDVCC high, or automatically in the event
of hardware faults. Hardware faults are over-current, overheating, VDD fault, VPC fault, VCC fault, and card
extraction during the session. To be noted that VPC and VCC faults are linked together so that a fault is generated
when VPC goes lower than VCC.
The following steps show the deactivation sequence and the timing of the card control signals when the system
controller sets the
CMDVCC high or OFF goes low due to a fault or card removal:
-
RST goes low at the end of t1.
-
CLK is set low at the end of t2.
-
I/O goes low at the end of t3. Out of reception mode.
-
VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.
RST
CLK
I/O
VCC
t
1
t
2
t
3
t
4
t
5
CMDVCC
-- OR--
OFF
t1 = > 0.5s, timing by 1.5MHZ internal Oscillator
t2 = > 7.5s
t3 = > 0.5s
t4 = > 0.5s
t5 = depends on VCC filter capacitor.
For NDS application, CF=1F makes t1 + t2 + t3 + t4 + t5 < 100s
Figure 4: Deactivation Sequence
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