參數(shù)資料
型號： 73S8024C-ILR/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： LEAD FREE, SOP-28
文件頁數(shù)： 9/22頁
文件大?。?/td> 471K
代理商： 73S8024C-ILR/F
DS_8024C_023
73S8024C Data Sheet
Rev. 1.3
17
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC,
AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I//OUC, AUX1UC, and AUX2UC.
IIL requirements only pertain to I//OUC, AUX1UC, and AUX2UC.
V
Output level, high (I/O, AUX1,
AUX2)
OH
IOH
0.9 V
= 0
CC
VCC
V
+ 0.1
IOH
0.75 V
= -40
A
CC
VCC
V
+ 0.1
V
Output level, high (I/OUC,
AUX1UC, AUX2UC)
OH
IOH
0.9 V
= 0
DD
VDD
V
+ 0.1
IOH
0.75 V
= -40
A
DD
VDD
V
+ 0.1
V
Output level, low
OL
IOL = 1 mA
0.3
V
Input level, high (I/O, AUX1,
AUX2)
IH
1.8
VCC
V
+ 0.30
V
Input level, high (I/OUC,
AUX1UC, AUX2UC)
IH
1.8
VDD
V
+ 0.30
V
Input level, low
IL
-0.3
0.8
V
Output voltage when outside
of session
INACT
IOL = 0
0.1
V
IOL = 1 mA
0.3
V
I
Input leakage
LEAK
VIH = VCC
10
A
I
Input current, low
IL
VIL = 0, CS = 1
0.65
mA
VIL = 0, CS = 0
5
μA
I
Short circuit output current
SHORTL
For output low,
shorted to VCC
through 33
15
mA
I
Short circuit output current
SHORTH
For output high,
shorted to ground
through 33
15
mA
tR, t
Output rise time, fall times
F
CL = 80 pF, 10% to
90%. For I/OUC,
AUX1UC, AUX2UC,
CL = 50 pF
100
ns
tIR, t
Input rise, fall times
IF
1
s
R
Internal pull-up resistor
PU
Output stable for
> 200ns
8
11
14
k
FD
Maximum data rate
MAX
1
MHz
T
Delay, I/O to I/OUC,
I/OUC to I/O
(falling edge to falling edge)
FDIO
100
ns
C
Input capacitance
IN
10
pF
Reset and Clock for card interface, RST, CLK
V
Output level, high
OH
IOH
0.9 V
= -200
A
CC
V
CC
V
Output level, low
OL
IOL
0
= 200
A
0.3
V
Output voltage when outside
of a session
INACT
IOL = 0
0.1
V
IOL = 1 mA
0.3
V
I
Output current limit, RST
RST_LIM
30
mA
I
Output current limit, CLK
CLK_LIM
70
mA
tR, t
Output rise time, fall time
F
CL = 35 pF for CLK,
10% to 90%
8
ns
CL = 200 pF for RST,
10% to 90%
100
ns
δ
Duty cycle for CLK, except for f
= f
C
XTAL
L =35 pF,
FCLK
45
≤ 20 MHz
55
%
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