參數(shù)資料
型號(hào): 73S8010C-IMR
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, QCC32
封裝: 5 X 5 MM, QFN-32
文件頁(yè)數(shù): 4/27頁(yè)
文件大小: 367K
代理商: 73S8010C-IMR
73S8010C
Smart Card Interface
DATA SHEET
Page: 12 of 27
2005 TERIDIAN Semiconductor Corporation
Rev 1.2
Deactivation Sequence:
Deactivation is initiated either by the system controller by resetting the Start/Stop bit, or automatically in the event
of hardware faults. Hardware faults are over-current, over-temperature, VDD fault, VPC fault, VCC fault, and card
extraction during the session.
The following steps show the deactivation sequence and the timing of the card control signals when the system
controller clears the Start/Stop bit:
-
RST goes low at the end of t1.
-
CLK goes low at the end of t2.
-
I/O goes low at the end of t3. Out of reception mode.
-
Shut down VCC at the end of time t4.
Start/Stop
RST
CLK
IO
VCC
t
1
t
2
t
3
t
4
t1 = > .5s
t2 = > 7.5s
t3 = > 0.5s
t4 = > 0.5s
Figure 7 - De-activation Sequence
Interrupt:
Interrupt is an active low interrupt. It is set low if any of these internal faults are detected:
- VCC fault
- VDD fault
- VPC fault
Or if one of these status bits condition is detected:
-Early ATR
-Mute ATR
-Card insert or card extract
-Protection status from Over-current or Over-heating
In case the interrupt is set low by the detection of these status bits, then the interrupt is set high when these
status bits are read. (READ STATUS DONE)
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