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參數(shù)資料
| 型號(hào)： | 73S1215F-68IM/F/P |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 130/136頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SMART CARD READER PROG 68-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | 73S12xx |
| 核心處理器： | 80515 |
| 芯體尺寸： | 8-位 |
| 速度： | 24MHz |
| 連通性： | I²C，智能卡，UART/USART，USB |
| 外圍設(shè)備： | LED，POR，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 64KB（64K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 包裝： | 管件 |
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DS_1215F_003
73S1215F Data Sheet
Rev. 1.4
93
TX Control/Status Register (STXCtl): 0xFE06
0x00
This register is used to control transmission of data to the smart card. Some control and some status bits
are in this register.
Table 86: The STXCtl Register
MSB
LSB
I2CMODE
–
TXFULL TXEMTY TXUNDR LASTTX
TX/RXB BREAKD
Bit
Symbol
Function
STXCtl.7
I2CMODE
I2C Mode – When in sync mode and this bit is set, and when the RLen count
value = max or 0, the source of the smart card data for IO pin (or SIO pin) will
FIFO. See the description for the Protocol Mode Register for more detail.
STXCtl.6
–
STXCtl.5
TXFULL
TX FIFO is full. Additional writes may corrupt the contents of the FIFO. This
bit it will remain set as long as the TX FIFO is full. Generates TX_Event
interrupt upon going full.
STXCtl.4
TXEMTY
1 = TX FIFO is empty, 0 = TX FIFO is not empty. If there is data in the TX
FIFO, the circuit will transmit it to the smart card if in transmit mode. In T=1
mode, if the LASTTX bit is set and the hardware is configured to transmit the
CRC/LRC, the TXEMTY will not be set until the CRC/LRC is transmitted. In
T=0, if the LASTTX bit is set, TXEMTY will be set after the last word has
been successfully transmitted to the smart card. Generates TXEVNT
interrupt upon going empty.
STXCtl.3
TXUNDR
TX Underrrun – (Read only) Asserted when a transmit under-run condition
has occurred. An under-run condition is defined as an empty TX FIFO when
the last data word has been successfully transmitted to the smart card and
the LASTTX bit was not set. No special processing is performed by the
hardware if this condition occurs. Cleared when read by firmware. This bit
generates TXERR interrupt.
STXCtl.2
LASTTX
Last TX Byte – Set by firmware (in both T=0 and T=1) when the last byte in
the current message has been written into the transmit FIFO. In T=1 mode,
the CRC/LRC will be appended to the message. Should be set after the last
byte has been written into the transmit FIFO. Should be cleared by firmware
before writing first byte of next message into the transmit FIFO. Used in T=0
to determine when to set TXEMTY.
STXCtl.1
TX/RXB
1 = Transmit mode, 0 = Receive mode. Configures the hardware to be
receiving from or transmitting to the smart card. Determines which counters
should be enabled. This bit should be set to receive mode prior to switching
to another interface. Setting and resetting this bit shall initialize the CRC
logic. If LASTTX is set, this bit can be reset to RX mode and UART logic will
automatically change mode to RX when TX operation is completed
(TX_Empty =1).
STXCtl.0
BREAKD
Break Detected – (Read only) 1 = A break has been detected on the I/O line
indicating that the smart card detected a parity error. Cleared when read.
This bit generates TXERR interrupt.
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