參數(shù)資料
型號(hào): 73S1215F-44IM/F/P
廠商: Maxim Integrated Products
文件頁數(shù): 121/136頁
文件大?。?/td> 0K
描述: IC SMART CARD READER PROG 44-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 260
系列: 73S12xx
核心處理器: 80515
芯體尺寸: 8-位
速度: 24MHz
連通性: I²C,智能卡,UART/USART,USB
外圍設(shè)備: LED,POR,WDT
輸入/輸出數(shù): 9
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤
包裝: 管件
DS_1215F_003
73S1215F Data Sheet
Rev. 1.4
85
RLength Count - was set for length of ATR
CLK
IO
RLength Interrupt
CLK Stop
CLK Stop Level
IO Bit
IODir Bit
TX/RX Mode Bit
TX = '1'
Data from Card -end of ATR
Data from TX FIFO
RLength
Count MAX
1. Interrupt generated when Rlength counter is MAX.
2. Read and clear Interrupt.
3. Set CLK Stop and CLK Stop level high in Interrupt routine.
4. Set TX/RX Bit to TX mode.
5. Reload Rlength Counter.
6. Set IO Bit low and IODir = Output. Since Rlen=(MAX or 0) and TX/RX =1, IO pin is controlled by IO bit.
7. Clear CLK Stop and CLK Stop level.
Note: Data in TX fifo should not be Empty here.
START Bit
Synchronous Clock Start/Stop Mode style Start bit procedure. This procedure should be used to
generate the start bit insertion in Synchronous mode for Synchronous Clock Start/Stop Mode protocol.
RLen=0
Rlen=1
2
1
3
7
6
5
6
4
Figure 23: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode
RLength Count
(Rlength = 9)
CLK
IO
RLength Interrupt
CLK Stop
CLK Stop Level
IO Bit
IODir Bit
TX/RX Mode Bit
TX = '1'
I2CMode = 1: Data to/from Card
I2CMode = 0: Data from TX fifo
I2CMode = 1:ACK Bit (to/from card)
I2CMode = 0: Data from TX fifo
RLength Count MAX
1. Interrupt generated when Rlength counter is MAX.
2. Read and clear Interrupt.
3. Set CLK Stop and CLK Stop level high, set IO Bit low and IODir = Output.
4. Set IO Bit High and IODir = Output.
5. Set TX/RX Bit to RX mode.
6. Reload Rlength Counter.
7. Clear CLK Stop and CLK Stop level.
STOP Bit
Synchronous Clock Start/Stop Mode Stop bit procedure. This procedure should be used to
generate the Stop bit in Synchronous Mode.
1
2
4
3
5
7
6
Min ETU
Figure 24: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode
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