參數(shù)資料
型號： 73S1210F-44IM/F/P
廠商： Maxim Integrated Products
文件頁數(shù)： 41/126頁
文件大小： 0K
描述： IC SMART CARD READER PROG 44-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 260
系列： 73S12xx
核心處理器： 80515
芯體尺寸： 8-位
速度： 24MHz
連通性： I²C，智能卡，UART/USART
外圍設(shè)備： LED，POR，WDT
輸入/輸出數(shù)： 8
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 6.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-VFQFN 裸露焊盤
包裝： 管件
DS_1210F_001
73S1210F Data Sheet
Rev. 1.4
21
Program Status Word (PSW):
Table 9: PSW Register
MSB
LSB
CV
AC
F0
RS1
RS
OV
–
P
Bit
Symbol
Function
PSW.7
CV
Carry flag.
PSW.6
AC
Auxiliary Carry flag for BCD operations.
PSW.5
F0
General purpose Flag 0 available for user.
PSW.4
RS1
Register bank select control bits. The contents of RS1 and RS0 select the
working register bank:
RS1/RS0
Bank Selected
Location
00
Bank 0
(0x00 – 0x07)
01
Bank 1
(0x08 – 0x0F)
10
Bank 2
(0x10 – 0x17)
11
Bank 3
(0x18 – 0x1F)
PSW.3
RS0
PSW.2
OV
Overflow flag.
PSW.1
F1
General purpose Flag 1 available for user.
PSW.0
P
Parity flag, affected by hardware to indicate odd / even number of “one” bits
in the Accumulator, i.e. even parity.
Stack Pointer: The stack pointer (SP) is a 1-byte register initialized to 0x07 after reset. This register is
incremented before PUSH and CALL instructions, causing the stack to begin at location 0x08.
Data Pointer: The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH.
It can be loaded as a 2-byte register (MOV DPTR,#data16) or as two registers (e.g. MOV DPL,#data8). It
is generally used to access external code or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR
respectively).
Program Counter: The program counter (PC) is 2 bytes wide initialized to 0x0000 after reset. This
register is incremented during the fetching operation code or when operating on data from program
memory. Note: The program counter is not mapped to the SFR area.
Port Registers: The I/O ports are controlled by Special Function Register USR70. The contents of the
SFR can be observed on corresponding pins on the chip. Writing a 1 to any of the ports (see Table 10)
causes the corresponding pin to be at high level (3.3V), and writing a 0 causes the corresponding pin to
be held at low level (GND). The data direction register UDIR70 define individual pins as input or output
pins (see the User (USR) Ports section for details).
Table 10: Port Registers
Register
SFR
Address
R/W
Description
USR70
0x90
R/W
Register for User port bit 7:0 read and write operations (pins USR0…
USR7).
UDIR70
0x91
R/W
Data direction register for User port bits 0:7. Setting a bit to 0 means
that the corresponding pin is an output.
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