參數(shù)資料
型號(hào): 73M1866B-IMR/F
廠商: Maxim Integrated Products
文件頁數(shù): 54/88頁
文件大?。?/td> 0K
描述: MICRODAA SGL PCM HIGHWAY 42-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: MicroDAA™
功能: 數(shù)據(jù)存取裝置(DAA)
接口: PCM,串行,SPI
電路數(shù): 1
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 42-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 42-QFN(8x8)
包裝: 帶卷 (TR)
包括: PCM 通路
73M1866B/73M1966B Data Sheet
DS_1x66B_001
58
Rev. 1.6
TX Level
Analog Gain
Digital Gain
Ana+Dig
dBm
TxBst DAA1 DAA0 dB
TXDG
dB
-17
0
1
-8
1001_1010
-8.75
-16.75
-16
0
1
-8
1010_0110
-7.75
-15.75
-15
0
1
-8
1010_1110
-6.75
-14.75
-14
0
1
-8
0100_0010
-5.75
-13.75
-13
0
1
-8
0100_1010
-4.75
-12.75
-12
0
1
-8
0101_0010
-3.75
-11.75
-11
0
1
-8
0101_1010
-2.75
-10.75
-10
0
1
-8
0110_0110
-1.75
-9.75
-9
0
1
-8
0110_1110
-0.75
-8.75
-8
0
1
-8
0000_0010
0.25
-7.75
-7
0
1
-8
0000_1010
1.25
-6.75
-6
0
1
0
-4
0110_0110
-1.75
-5.75
-5
0
1
0
-4
0110_1110
-0.75
-4.75
-4
0
1
0
-4
0000_0010
0.25
-3.75
-3
0
1
0
-4
0000_1010
1.25
-2.75
-2
1
-2
0000_0010
0.25
-1.75
-1
0
1
0
0110_1110
-0.75
0
1
0
0000_0010
0.25
1
0
1
0
0000_1010
1.25
2
1
0
2
0000_0010
0.25
2.25
3
0
3
0000_0010
0.25
3.25
4
0
3
0000_1010
1.25
4.25
5
1
0
6
0110_1110
-0.75
5.25
6
1
0
6
0000_0010
0.25
6.25
Note (1)
1
0
6
0000_1010
1.25
7.25
Note (1)
1
0
6
0001_0010
2.25
8.25
Note (1)
1
0
6
0001_1010
3.25
9.25
Note (1)
1
0
6
0010_0110
4.25
10.25
Note (1)
1
0
6
0010_1110
5.25
11.25
Note (1)
1
0
6
0011_0110
6.25
12.25
Note 1. Tx Data is assumed small enough that the combination of Tx Data and TXDG is less than 1.25 dBm.
8.8.1.2 Receive Gain Scaling
On the receive side, a 0 dBm receive signal on the line results in ~0 dBm at the PCM interface.
Means is provided to adjust receive signal path gain by use of a digital gain stage. This gain value is
controlled by Register 0x09[7:0] (RXDG). The gain values are explained in Table 33.
The two RXG bits (Register 0x14[1:0]) control the value of the receiver analog gain. The RXG bits must
be set to 10 to enable 0 dB gain in the receive path.
For the best S/N performance it is recommended to use a gain value up front in the analog domain. The
digital control should be used to fine-tune the receiver signal path gain.
When the received line signal exceeds a voltage level greater than specified by ITU-T
Recommendation G.711, the receive gain must be reduced to prevent saturation and clipping within
the receive signal processing path.
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