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參數(shù)資料
| 型號(hào)： | 73LDI-4L20 |
| 英文描述： | Converter |
| 中文描述： | 轉(zhuǎn)換器 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 23K |
| 代理商： | 73LDI-4L20 |
Apex Signal, A Division of NAI, Inc.
Bohemia, NY 11716 USA
www.naii.com
Code: 0VGU1
Model PC104-73LD1 Specifications
PC104-73LD1 Rev E
SHEET 3 OF 4
Offset: Page 3 (Offset 1F = 2)
00 Save
02 Latch
04 Exc. Ch.1 Lo read/write 09 Exc. Ch.3 Hi
05 Exc. Ch.1 Hi read/write 0A Exc. Ch.4 Lo read/write 0F Sig. Ch.2 Hi read/write
06 Exc. Ch.2 Lo read/write 0B Exc. Ch.4 Hi
write 07 Exc. Ch.2 Hi
write 08 Exc. Ch.3 Lo read/write 0D Sig. Ch.1 Hi read/write
read/write 0E Sig. Ch.2 Lo read/write
read/write 0C Sig. Ch.1 Lo read/write
11 Sig. Ch.3 Hi
12 Sig. Ch.4 Lo
13 Sig. Ch.4 Hi
14
Power-On (POST) enableread/write
1F 2
read/write
read/write
read/write
read/write 10 Sig. Ch.3 Lo read/write
read/write
Hi byte
D13
Lo byte
D6
D15
Sign 5.000 2.500 1.250 .6250 .3125 .1563 .0781 .0391 .0195 .0098 .0049 .0024. .0012 .0006 .0003
Data, Velocity (rps) Sign
D
D
D
D
D
D
Latch outputs
X
X
X
X
X
X
X
Test Enable
X
X
X
X
X
X
X
Active channels
X
X
X
X
X
X
X
Status, signal
X
X
X
X
X
X
X
Status, excitation
X
X
X
X
X
X
X
Status, Test
X
X
X
X
X
X
X
D14
D12
D11
D10
D9
D8
D7
D5
D4
D3
D2
D1
D0
Data
D
X
X
X
X
X
X
D
X
X
X
X
X
X
D
X
X
X
X
X
X
D
X
X
X
X
X
X
D
X
X
X
X
X
X
D
X
D3
Ch.4
Ch.4
Ch.4
Ch.4
D
X
D2
Ch.3
Ch.3
Ch.3
Ch.3
D
1
X
D
X
D0
Ch.1
Ch.1
Ch.1
Ch.1
Ch.2
Ch.2
Ch.2
Ch.2
Power ON
or system reset,
unless POST (Page 3, 1Eh is set to (“1”) and saved,
disables D3 test, all
channels unlatched, excitation supply frequency to 400 Hz and output voltage to zero. Program required frequency
before increasing output voltage.
Enter all active channels
at Page 3, 1Ah “1” =active; “0” =not used. Omitting this step will produce false
alarms because unused channels will set faults. To
save
when all channels are programmed, write 5555h at Page
1, 1Ah. Board will clear to hex 00 when save is completed. These settings will repeat until changed. Saving is
optional. If not saved, reenter at each power on. To restore factory shipped parameters, write AAAAh at Page 1,
1Ah, wait until board writes 00, then do a system reset.
Data Format:
Two's complement. Sign: (D15) 0=In Phase; 1= Out of Phase. Offset Binary (two’s complement
with MSB inverted) can be specified. (see part number) The output represents A-B/A+B. Max. positive excursion is
7FFF, 0=0, and max. negative excursion is 8000.
Programming
Signal and Reference
:
The LVDT primary, as usual, is energized by either the excitation
output from this card or from an external excitation.
The
signal voltage
to be programmed represents the max. output voltage of the LVDT. The 4-wire LVDT has
two output voltages referred to as A and B. When connected to the A and B Signal inputs no scaling is required
because the inputs are Autoranging. For 2-wire LVDT’s scaling is required as follows:
Set Excitation and Signal voltages by writing a 16 bit binary word to the appropriate address.
Ex
: 27.11 V Signal to Ch.2 =
0000101010010111 to Page 2, 02h/03h
26.00 V Excitation to Ch.2 = 0000101000101000 to Page 3, 02h/03h.
(A+B) output:
Read binary number and multiply by 0.01 Volt.
Velocity:
16 bit resolution, (15 bit+sign, 2’s compliment); Linearity: 0.1%.
If velocity scale factor is set to max. (FFFFh), then 1 bit of velocity output = 0.4% FS/sec. Ex: If full stroke is
±
3” (6”
total) and you read a velocity output of 630h, then the velocity is 630 x 0.004 x 6 = 15.12 inches/sec
Status, Test:
“1” Accuracy OK; “0” failed.
Status:
“1” Exc. & Signal are On; “0” Exc. and/or Signal loss.
Test Enable (D2):
Writing “1” to D2 at Page 2, 1Eh,
initiates automatic background bit testing Each channel is
checked over the programmed Signal range to a measuring accuracy 0.1%FS, and each Signal and Excitation is
monitored. The results are available in status registers. A “0” deactivates this test. The testing is totally
transparent to the user, requires no external programming, has no effect on the standard operation of this card and
can be enabled or disabled via the bus. Card will write hex 55 at Page 3, 18h when (D2) is enabled. User can
periodically clear to hex 00 and then read Page 3, 18h again to verify that background bit testing is activated.
Test Enable (D3):
Power-on (POST) if enabled, or
writing “1” to D3 at Page 2, 1Eh,
starts
an initiated bit test
that disconnects all channels from the outside world and connects them across an internal stimulus that
generates multiple test voltages that are measured to a test accuracy and of 0.1%FS. Test cycle takes about 10
seconds and results can be read from registers when D3 changes from “1” to “0”. External excitation is not
required. Testing is totally transparent to the user, requires no external programming, and can be enabled or
disabled (by setting D3 to “0”) via the bus.
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