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參數(shù)資料
| 型號： | 72V3612L12PQF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 64 X 36 BI-DIRECTIONAL FIFO, 8 ns, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 240K |
| 代理商： | 72V3612L12PQF |
5
IDT72V3612 3.3V, CMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O
Description
MBF2
Mail2 Register Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
Writes to the mail2 register are inhibited while
MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-
HIGH transition of CLKA when a port A read is selected and MBA is HIGH.
MBF2 is set HIGH
when the device is reset.
ODD/
Odd/Even Parity
I
Odd parity is checked on each port when ODD/
EVEN is HIGH, and even parity is checked when
EVEN
Select
ODD/
EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity
generation is enabled for a read operation.
PEFA
Port A Parity Error
O
When any byte applied to terminals A0-A35 fails parity,
PEFA is LOW. Bytes are organized as
Flag
(Port A)
A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the
parity bit. The type of parity checked is determined by the state of the ODD/
EVEN input. The
parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if
parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by
having W/
RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the
A0-A35 inputs.
PEFB
Port B Parity Error
O
When any byte applied to terminals B0-B35 fails parity,
PEFB is LOW. Bytes are organized as
Flag
(Port B)
B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity
bit. The type of parity checked is determined by the state of the ODD/
EVEN input. The parity trees
used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity
generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having
W/
RB LOW, MBB HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless of the state of
the B0-B35 inputs.
PGA
Port A Parity
I
Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is
Generation
selected by the state of the ODD/
EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26,
and A27-A35. The generated parity bits are output in the most significant bit of each byte.
PGB
Port B Parity
I
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is
Generation
selected by the state of the ODD/
EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26,
and B27-B35. The generated parity bits are output in the most significant bit of each byte.
RST
Reset
I
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of
CLKB must occur while
RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and
the
EFA, EFB, AEA, AEB, FFA, and FFB flags LOW. The LOW-to-HIGH transition of RST latches
the status of the FS1 and FS0 inputs to select Almost-Full and Almost-Empty flag offset.
W/
RA
Port A Write/Read
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-
Select
HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/
RA is
HIGH.
W/
RB
Port B Write/Read
I
A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-
Select
HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/
RB is
HIGH.
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PDF描述 |
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| IDT72V3612L12PQF | 3.3 VOLT CMOS SyncBiFIFO-TM 64 x 36 x 2 |
| IDT72V3612L15PF | 3.3 VOLT CMOS SyncBiFIFO-TM 64 x 36 x 2 |
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| IDT72V3612L20PQF | 3.3 VOLT CMOS SyncBiFIFO-TM 64 x 36 x 2 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 72V3612L15PF | 功能描述:IC FIFO 64X36X2 15NS 120QFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):過期 存儲容量:4.5K（64 x 36 x 2） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:- 總線方向:雙向 擴充類型:寬 可編程標(biāo)志支持:是 中繼能力:無 FWFT 支持:無 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標(biāo)準(zhǔn)包裝:45 |
| 72V3612L15PF8 | 功能描述:IC FIFO 64X36X2 15NS 120QFP 制造商:idt, integrated device technology inc 系列:72V 包裝:帶卷（TR） 零件狀態(tài):過期 存儲容量:4.5K（64 x 36 x 2） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:- 總線方向:雙向 擴充類型:寬 可編程標(biāo)志支持:是 中繼能力:無 FWFT 支持:無 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標(biāo)準(zhǔn)包裝:750 |
| 72V3612L20PF | 功能描述:IC FIFO 64X36X2 20NS 120QFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):過期 存儲容量:4.5K（64 x 36 x 2） 功能:同步 數(shù)據(jù)速率:50MHz 訪問時間:12ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:- 總線方向:雙向 擴充類型:寬 可編程標(biāo)志支持:是 中繼能力:無 FWFT 支持:無 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標(biāo)準(zhǔn)包裝:45 |
| 72V3612L20PF8 | 功能描述:IC FIFO 64X36X2 20NS 120QFP 制造商:idt, integrated device technology inc 系列:72V 包裝:帶卷（TR） 零件狀態(tài):過期 存儲容量:4.5K（64 x 36 x 2） 功能:同步 數(shù)據(jù)速率:50MHz 訪問時間:12ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:- 總線方向:雙向 擴充類型:寬 可編程標(biāo)志支持:是 中繼能力:無 FWFT 支持:無 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標(biāo)準(zhǔn)包裝:750 |
| 72V3613L12PF | 功能描述:IC FIFO CLOCK 64X36 12NS 120TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):過期 存儲容量:2.25K（64 x 36） 功能:同步 數(shù)據(jù)速率:83MHz 訪問時間:8ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:- 總線方向:雙向 擴充類型:寬 可編程標(biāo)志支持:是 中繼能力:無 FWFT 支持:無 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標(biāo)準(zhǔn)包裝:45 |
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