參數(shù)資料
型號: 72V285L15TFI9
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 64K X 18 OTHER FIFO, 10 ns, PQFP64
封裝: STQFP-64
文件頁數(shù): 17/25頁
文件大小: 266K
代理商: 72V285L15TFI9
24
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
Figure 20. Block Diagram of 65,536 x 18 and 131,072 x 18 Depth Expansion
Forafullexpansionconfiguration,theamountoftimeittakesfor
IRofthefirst
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock, for the
IRflag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
end of the chain and free locations to the beginning of the chain.
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
IDT
72V275
72V285
TRANSFER CLOCK
4512 drw 23
n
FWFT/SI
IDT
72V275
72V285
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