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| 型號(hào)： | 71M6534H-IGTR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP120 |
| 封裝： | LEAD FREE, LQFP-120 |
| 文件頁(yè)數(shù)： | 33/124頁(yè) |
| 文件大小： | 2008K |
| 代理商： | 71M6534H-IGTR/F |
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71M6533/71M6534 Data Sheet
FDS_6533_6534_004
16
2007-2009 TERIDIAN Semiconductor Corporation
v1.1
1.2.12 Pulse Generators
The 71M6533 and 71M6534 provide four pulse generators, RPULSE, WPULSE, XPULSE and YPULSE,
as well as hardware support for the RPULSE and WPULSE pulse generators. The pulse generators can
be used to output CE status indicators, SAG for example, to DIO pins.
The polarity of the pulses may be inverted with PLS_INV. When this bit is set, the pulses are active high,
rather than the more usual active low. PLS_INV inverts all the pulse outputs.
XPULSE and YPULSE
Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse outputs. Pins DIO8
and DIO9 are used for these pulses. Generally, the XPULSE and YPULSE outputs are updated once on
each pass of the CE code, resulting in a pulse frequency up to a maximum of 1260Hz (assuming a MUX
frame is 13 CK32 cycles).
Standard CE code permits the selection of either an energy indication or signaling of a sag event for the
YPULSE output. See Section 4.3 CE Interface Description for details.
RPULSE and WPULSE
During each CE code pass, the hardware stores exported WPULSE AND RPULSE sign bits in an 8-bit FIFO
and outputs them at a specified interval. This permits the CE code to calculate the RPULSE and WPULSE
outputs at the beginning of its code pass and to rely on hardware to spread them over the MUX frame. The
FIFO is reset at the beginning of each MUX frame. PLS_INTERVAL[7:0] controls the delay to the first pulse
update and the interval between subsequent updates. The LSB of PLS_INTERVAL[7:0] is equivalent to 4
CK_FIR cycles. If zero, the FIFO is deactivated and the pulse outputs are updated immediately. Thus,
NINTERVAL is 4*PLS_INTERVAL.
Since the FIFO resets at the beginning of each MUX frame, the user must specify PLS_INTERVAL so that
all of the pulse updates are output before the MUX frame completes. For instance, if the CE code outputs
6 updates per MUX interval, and if the MUX interval is 1950 cycles long, the ideal value for the interval is
1950/6/4 = 81.25. If PLS_INTERVAL = 82, the fifth output will occur too late and be lost. In this case, the
proper value for PLS_INTERVAL is 81.
Hardware also provides a maximum pulse width feature: PLS_MAXWIDTH[7:0] selects a maximum nega-
tive pulse width to be Nmax updates according to the formula: Nmax = (2*PLS_MAXWIDTH+1). If
PLS_MAXWIDTH=255, no width checking is performed.
The WPULSE and RPULSE pulse generator outputs are available on DIO6 and DIO7, respectively. They
can also be output on OPT_TX (see OPT_TXE[1:0] for details).
1.2.13 Data RAM (XRAM)
In the 71M6533/71M6534, the CE and MPU use a single general-purpose Data RAM (also referred to as
XRAM). The Data RAM is 1024 32-bit words, shared between the CE and the MPU using a time-multi-
plex method. This reduces MPU wait states when accessing CE data. When the MPU and CE are clock-
ing at maximum frequency (10 MHz), the DRAM will make up to four accesses during each 100 ns inter-
val. These consist of two MPU accesses, one CE access and one SPI access.
The Data RAM is 32 bits wide and uses an external multiplexer so as to appear byte-wide to the MPU.
The Data RAM hardware will convert an MPU byte write operation into a read-modify-write operation that
requires two Data RAM accesses. The second access is guaranteed to be available because the MPU
cannot access the XRAM on two consecutive instructions unless it is using the same address.
In addition to the reduction of wait states, this arrangement permits the MPU to easily use unneeded CE data
memory. Likewise, the amount of memory the CE uses is not limited by the size of a dedicated CE data RAM.
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