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| 型號(hào)： | 71M6534H-IGT/F |
| 廠商： | TERIDIAN SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP120 |
| 封裝： | LEAD FREE, LQFP-120 |
| 文件頁(yè)數(shù)： | 119/124頁(yè) |
| 文件大?。?/td> | 2008K |
| 代理商： | 71M6534H-IGT/F |
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71M6533/71M6534 Data Sheet
FDS_6533_6534_004
94
2007-2009 TERIDIAN Semiconductor Corporation
v1.1
The EXT_TEMP bit enables temperature compensation by the MPU, when set to 1. When 0, internal (CE)
temperature compensation is enabled.
I0_SHUNT, I1_SHUNT and I2_SHUNT can configure their respective current inputs to accept shunt resistor
sensors. In this case the CE provides an additional gain of 8 to the selected current input. WRATE may
need to be adjusted based on the values In_SHUNT.
The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by
the MPU if EXT_PULSE = 1. In this case, the MPU controls the pulse rate by placing values into APULSEW
and APULSER. By setting EXT_PULSE = 0, the CE controls the pulse rate based on WSUM and VARSUM.
The 71M6533 Demo Code creep function halts both internal and external pulse generation.
Table 53: CECONFIG Bit Definitions
CECONFIG
[bit]
Name
Default
Description
[20]
SAG_MASK2
0
When 1, enables sag interrupt based on phase C.
[19]
SAG_MASK1
0
When 1, enables sag interrupt based on phase B.
[18]
SAG_MASK0
0
When 1, enables sag interrupt based on phase A.
[17]
SAG_INT
0
When 1, activates YPULSE/DIO8 output when a sag is de-
tected (see also 1.4.7).
[16]
EXT_TEMP
0
When 1, enables temperature compensation by the MPU.
When 0, internal (CE) temperature compensation is enabled.
[15:8]
SAG_CNT
80
(0x50)
The number of consecutive voltage samples below SAG_THR
before a sag alarm is declared. The maximum value is 255.
SAG_THR is at address 0x24.
[7]
FREQSEL1
0
The combination of FREQSEL1 and FEQSEL2 selects the
phase to be used for the frequency monitor, the phase-to-
phase lag calculation and for the zero crossing counter
(MAINEDGE_X).
FREQ
SEL1
FREQ
SEL0
Phase
Se-
lected
Phases Used for Voltage
Phase Lag Calculation
PH_AtoB_X
PH_AtoC_X
0
A
A-B
A-C
0
1
B
B-C
B-A
1
0
C
C-A
C-B
1
Not allowed
[6]
FREQSEL0
0
[5]
EXT_PULSE
1
When zero, causes the pulse generators to respond to internal
data (WPULSE = WSUM_X, RPULSE = VARSUM_X,
XPULSE = WSUM_X). Otherwise, the generators respond to
values the MPU places in APULSEW and APULSER.
[4]
IC_SHUNT
0
When 1, the current gain of channel C is increased by 8. The
gain factor controlled by In_SHUNT is referred to as In_8
throughout this document.
[3]
IB_SHUNT
0
When 1, the current gain of channel B is increased by 8.
[2]
IA_SHUNT
0
When 1, the current gain of channel A is increased by 8.
[1]
PULSE_FAST
0
When PULSE_FAST = 1, the pulse generator input is increased
16x. When PULSE_SLOW = 1, the pulse generator input is
reduced by a factor of 64. These two parameters control the
pulse gain factor X (see table below). Allowed values are ei-
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