參數(shù)資料
型號： 71M6534H-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP120
封裝： LEAD FREE, LQFP-120
文件頁數(shù)： 46/124頁
文件大?。?/td> 2008K
代理商： 71M6534H-IGT/F
71M6533/71M6534 Data Sheet
FDS_6533_6534_004
28
2007-2009 TERIDIAN Semiconductor Corporation
v1.1
S1CON. It is also recommended to have a timeout slightly longer than one character time on both inter-
rupts that restarts the transmit or receive logic.
Table 17: The S0CON (UART0) Register (SFR 0x98)
Bit
Symbol
Function
S0CON[7]
SM0
The SM0 and SM1 bits set the UART0 mode:
Mode
Description
SM0
SM1
0
N/A
0
1
8-bit UART
0
1
2
9-bit UART
1
0
3
9-bit UART
1
S0CON[6]
SM1
S0CON[5]
SM20
Enables the inter-processor communication feature.
S0CON[4]
REN0
If set, enables serial reception. Cleared by software to disable reception.
S0CON[3]
TB80
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the
MPU, depending on the function it performs (parity check, multiprocessor
communication etc.)
S0CON[2]
RB80
In Modes 2 and 3 it is the 9
th data bit received. In Mode 1, SM20 is 0,
RB80 is the stop bit. In mode 0, this bit is not used. Must be cleared by
software.
S0CON[1]
TI0
Transmit interrupt flag; set by hardware after completion of a serial trans-
fer. Must be cleared by software.
S0CON[0]
RI0
Receive interrupt flag; set by hardware after completion of a serial recep-
tion. Must be cleared by software.
Table 18: The S1CON (UART1) Register (SFR 0x9B)
Bit
Symbol
Function
S1CON[7]
SM
Sets the baud rate and mode for UART1.
SM
Mode
Description
Baud Rate
0
A
9-bit UART
variable
1
B
8-bit UART
variable
S1CON[5]
SM21
Enables the inter-processor communication feature.
S1CON[4]
REN1
If set, enables serial reception. Cleared by software to disable reception.
S1CON[3]
TB81
The 9
th transmitted data bit in Mode A. Set or cleared by the MPU, de-
pending on the function it performs (parity check, multiprocessor commu-
nication etc.)
S1CON[2]
RB81
In Modes A and B, it is the 9
th data bit received. In Mode B, if SM21 is 0,
RB81 is the stop bit. Must be cleared by software
S1CON[1]
TI1
Transmit interrupt flag, set by hardware after completion of a serial trans-
fer. Must be cleared by software.
S1CON[0]
RI1
Receive interrupt flag, set by hardware after completion of a serial recep-
tion. Must be cleared by software.
Table 19: PCON Register Bit Description (SFR 0x87)
Bit
Symbol
Function
PCON[7]
SMOD
The SMOD bit doubles the baud rate when set
PCON[6:2]
–
Not used.
PCON[1]
STOP
Stops MPU flash access and MPU peripherals including timers and
UARTs when set until an external interrupt is received.
PCON[0]
IDLE
Stops MPU flash access when set until an internal interrupt is received.
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