參數(shù)資料
型號(hào)： 71M6533H-IGTR/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： LEAD FREE, LQFP-100
文件頁數(shù)： 112/124頁
文件大小： 2008K
代理商： 71M6533H-IGTR/F
71M6533/71M6534 Data Sheet
FDS_6533_6534_004
88
2007-2009 TERIDIAN Semiconductor Corporation
v1.1
SLEEP
20A9[6]
0
W
Puts the 71M6533/71M6534 into SLEEP mode. This bit is ignored if system power is
present. The 71M6533 and 71M6534 will wake when the autowake timer times out,
when the push button is pushed, when system power returns or when RESET goes
high.
SEL_IAN
SEL_IBN
SEL_ICN
SEL_IDN
20AC[1]
20AC[5]
20AD[1]
20AD[5]
0
R/W
When set to 1, selects differential mode for the corresponding current input (IA, IB, IC,
or ID). When 0, the input remains single-ended.
SLOT0_SEL[3:0]
SLOT1_SEL[3:0]
…
SLOT8_SEL[3:0]
SLOT9_SEL[3:0]
2090[3:0]
2090[7:4]
2094[3:0]
2094[7:4]
0
1
…
8
9
0
1
…
8
9
R/W
Primary multiplexer frame analog input selection. These bits map the selected input,
0-9 to the multiplexer state. The ADC output is always written to the memory location
corresponding to the input, regardless of which multiplexer state an input is mapped to
SLOT0_ALTSEL
[3:0]
SLOT1_ALTSEL
[3:0]
SLOT2_ALTSEL
[3:0]
…
SLOT8_ALTSEL
[3:0]
SLOT9_ALTSEL
[3:0]
2096[3:0]
2096[7:4]
2097[3:0]
…
209A[3:0]
209A[7:4]
10
1
11
…
8
9
10
1
11
…
8
9
R/W
Alternate multiplexer frame analog input selection. Maps the selected input, 0-11, to
the multiplexer state.
The additional inputs, 10 and 11 in the alternate frame are:
10 = TEMP
11 = VBAT
SP_ADDR[15:8]
SP_ADDR[7:0]
2072[7:0]
2073[7:0]
–
R
SPI Address. 16-bit address from the bus master.
SP_CMD
2071
–
R
SPI command. 8-bit command from the bus master.
SPE
2070[7]
0
R/W
SPI port enable. Enables the SPI interface on pins SEG3 through SEG5.
SPI_FLAG
20B1[4]
R/W
SPI interrupt flag. The flag is set by the hardware and is cleared by the firmware writ-
ing a 0. Firmware using this interrupt should clear the spurious interrupt indication dur-
ing initialization.
SUBSEC[7:0]
2014[7:0]
–
R
The remaining count, in terms of 1/256 RTC cycles, to the next one second boundary.
SUBSEC may be read by the MPU after the one second interrupt and before reaching
the next one second boundary. Setting RST_SUBSEC will clear SUBSEC.
SUM_CYCLES[5:0] 2001[5:0]
0
R/W
The number of pre-summer outputs summed in the final summer.
TMUX[4:0]
20AA[4:0]
2
–
R/W
Selects one of 32 signals for TMUXOUT. For details, see Section 1.4.13 Test Ports
相關(guān)PDF資料
PDF描述
71M6534-IGTR/F SPECIALTY ANALOG CIRCUIT, PQFP120
71M6534H-IGT/F SPECIALTY ANALOG CIRCUIT, PQFP120
71M6534-IGTR/F SPECIALTY ANALOG CIRCUIT, PQFP120
71M6533H-IGTR/F SPECIALTY ANALOG CIRCUIT, PQFP100
71M6533H-IGT/F SPECIALTY ANALOG CIRCUIT, PQFP100
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