參數(shù)資料
型號: 71M6533H-IGT/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP100
封裝: LEAD FREE, LQFP-100
文件頁數(shù): 68/124頁
文件大小: 2008K
代理商: 71M6533H-IGT/F
71M6533/71M6534 Data Sheet
FDS_6533_6534_004
48
2007-2009 TERIDIAN Semiconductor Corporation
v1.1
3:0
CNT[3:0]
W
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data will be read MSB first, and right
justified into the low order bits of EEDATA. If RD=0, CNT bits will be
sent MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA will simply obey the HiZ bit.
The timing diagrams in Figure 10 through Figure 14 describe the 3-wire EEPROM interface behavior. All
commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that
is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 10 through Figure 14
are then sent via EECTRL and EEDATA.
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM
will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should
then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to
a low-Z state.
Figure 10: 3-wire Interface. Write Command, HiZ=0.
Figure 11: 3-wire Interface. Write Command, HiZ=1
Figure 12: 3-wire Interface. Read Command.
SCLK (output)
BUSY (bit)
CNT Cycles (6 shown)
SDATA (output)
Write -- No HiZ
D2
D3
D4
D5
D6
D7
EECTRL Byte Written
INT5
SDATA output Z
(LoZ)
CNT Cycles (6 shown)
Write -- With HiZ
INT5
EECTRL Byte Written
SCLK (output)
BUSY (bit)
SDATA (output)
D2
D3
D4
D5
D6
D7
(HiZ)
(LoZ)
SDATA output Z
CNT Cycles (8 shown)
READ
D0
D1
D2
D3
D4
D5
INT5
D6
D7
EECTRL Byte Written
SCLK (output)
BUSY (bit)
SDATA (input)
SDATA output Z
(HiZ)
相關(guān)PDF資料
PDF描述
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71M6533-IGT/F SPECIALTY ANALOG CIRCUIT, PQFP100
71M6534-IGT/F SPECIALTY ANALOG CIRCUIT, PQFP120
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