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| 型號(hào)： | 71M6532F-IGTR/F |
| 廠商： | TERIDIAN SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100 |
| 封裝： | LEAD FREE, LQFP-100 |
| 文件頁(yè)數(shù)： | 30/120頁(yè) |
| 文件大?。?/td> | 2477K |
| 代理商： | 71M6532F-IGTR/F |
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FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
v1.3
2005-2010 TERIDIAN Semiconductor Corporation
17
Since the FIFO resets at the beginning of each MUX frame, the user must specify PLS_INTERVAL so that
all of the pulse updates are output before
Hardware also provides a maximum pulse width feature. The PLS_MAXWIDTH register selects a maximum
negative pulse width to be Nmax updates according to the formula: Nmax = (2*PLS_MAXWIDTH+1). If
PLS_MAXWIDTH = 255, no width checking is performed.
the MUX frame completes. For instance, if the CE code outputs
5 updates per MUX interval and if the MUX interval is 1950 cycles long, the ideal value for the interval is
1950/5/4 = 97.5. If PLS_INTERVAL = 98, the fifth output will occur too late and be lost. In this case, the
proper value for PLS_INTERVAL is 97.
The WPULSE and RPULSE pulse generator outputs are available on DIO6 and DIO7, respectively. They
can also be output on OPT_TX (see OPT_TXE[1:0] for details).
1.3.4
Data RAM (XRAM)
The CE and MPU use a single general-purpose Data RAM (also referred to as XRAM). The Data RAM is
1024 32-bit words, shared between the CE and the MPU using a time-multiplex method. This reduces
MPU wait states when accessing CE data. When the MPU and CE are clocking at maximum frequency
(10 MHz), the DRAM will make up to four accesses during each 100 ns interval. These consist of two
MPU accesses, one CE access and one SPI access.
The Data RAM is 32 bits wide and uses an external multiplexer so as to appear byte-wide to the MPU.
The Data RAM hardware will convert an MPU byte write operation into a read-modify-write operation that
requires two Data RAM accesses. The second access is guaranteed to be available because the MPU
cannot access the XRAM on two consecutive instructions unless it is using the same address.
In addition to the reduction of wait states, this arrangement permits the MPU to easily use unneeded CE
data memory. Likewise, the amount of memory the CE uses is not limited by the size of a dedicated CE
data RAM.
1.3.5
Delay Compensation
When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that
phase must be sampled at the same instant. Otherwise, the phase difference, Ф, introduces errors.
o
delay
o
delay
f
t
T
t
360
=
=
φ
Where f is the frequency of the input signal and tdelay is the sampling delay between voltage and current.
In traditional meter ICs, sampling is accomplished by using two A/D converters per phase (one for voltage
and the other one for current) controlled to sample simultaneously. Teridian’s patented Single-Converter
Technology
, however, exploits the 32-bit signal processing capability of its CE to implement “constant
delay” all-pass filters. These all-pass filters correct for the conversion time difference between the voltage
and the corresponding current samples that are obtained with a single multiplexed A/D converter.
The “constant delay” all-pass filters provide a broad-band delay
β, that is precisely matched to the differ-
ence in sample time between the voltage and the current of a given phase. This digital filter does not af-
fect the amplitude of the signal, but provides a precisely controlled phase response. The delay compen-
sation implemented in the CE aligns the voltage samples with their corresponding current samples by
routing the voltage samples through the all-
pass filter, thus delaying the voltage samples by β, resulting in
the residual phase error β – Ф. The residual phase error is negligible, and is typically less than ±1.5 milli-
degrees at 100Hz, thus it does not contribute to errors in the energy measurements.
1.3.6
CE Functional Overview
The ADC processes one sample per channel per multiplexer cycle. Figure 6 shows the timing of the
samples taken during one multiplexer cycle.
The number of samples processed during one accumulation cycle is controlled by PRE_SAMPS[1:0]
(IORAM 0x2001[7:6]) and SUM_CYCLES[5:0] (IORAM 0x2001[5:0]). The integration time for each energy
output is:
PRE_SAMPS[1:0] * SUM_CYCLES[5:0] / 2520.6, where 2520.6 is the sample rate [Hz]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| 71M6533 | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Energy Meter IC |
| 71M6533-DB | 功能描述:開(kāi)發(fā)板和工具包 - 8051 71M6533 Demo Brd RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評(píng)估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓: |
| 71M6533G | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Exceeds IEC 62053/ANSI C12.20 Standards |
| 71M6533G-IGTR/F | 功能描述:計(jì)量片上系統(tǒng) - SoC AC Power Monitoring SoC-Programd RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時(shí)鐘頻率:70 Hz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數(shù)量:12 片上 ADC: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel |
| 71M6533H | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Energy Meter IC |
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