參數(shù)資料
型號(hào): 71M6532F-IGT/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
封裝: LEAD FREE, LQFP-100
文件頁(yè)數(shù): 42/120頁(yè)
文件大?。?/td> 2477K
代理商: 71M6532F-IGT/F
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)當(dāng)前第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
28
2005-2010 TERIDIAN Semiconductor Corporation
v1.3
Bit
Symbol
Function
S1CON[2]
RB81
In Modes A and B, it is the 9
th data bit received. In Mode B, if SM21 is 0,
RB81 is the stop bit. Must be cleared by software
S1CON[1]
TI1
Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software.
S1CON[0]
RI1
Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software.
Table 19: PCON Register Bit Description (SFR 0x87)
Bit
Symbol
Function
PCON[7]
SMOD
The SMOD bit doubles the baud rate when set
PCON[6:2]
Not used.
PCON[1]
STOP
Stops MPU flash access and MPU peripherals including timers and
UARTs when set until an external interrupt is received.
PCON[0]
IDLE
Stops MPU flash access when set until an internal interrupt is received.
1.4.7
Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured
for counter or timer operations.
In timer mode, the register is incremented every 12 MPU clock cycles. In counter mode, the register is
incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0 and T1 are
the timer gating inputs derived from certain DIO pins, see Section 1.5.7 Digital I/O). Since it takes 2 machine
cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clock frequency (CKMPU).
There are no restrictions on the duty cycle, however to ensure proper recognition of the 0 or 1 state, an
input should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1, as shown in Table 20 and Table 21. The
TMOD Register, shown in Table 22, is used to select the appropriate mode. The timer/counter operation
is controlled by the TCON Register, which is shown in Table 23. Bits TR1 (TCON[6]) and TR0 (TCON[4]) in
the TCON register start their associated timers when set.
Table 20: Timers/Counters Mode Description
M1
M0
Mode
Function
0
Mode 0
13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 register
and the remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer
1, respectively). The 3 high order bits of TL0 and TL1 are held at zero.
0
1
Mode 1
16-bit Counter/Timer mode.
1
0
Mode 2
8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or
TH1, while TL0 or TL1 is incremented every machine cycle. When TL(x)
overflows, a value from TH(x) is copied to TL(x) (where x = 0 for
counter/timer 0 or 1 for counter/timer 1.
1
Mode 3
If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.
If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent
8-bit Timer/Counters.
In Mode 3, TL0 is affected by TR0 and gate control bits and sets the TF0 flag on overflow, while TH0
is affected by the TR1 bit and the TF1 flag is set on overflow.
Table 21 specifies the combinations of operation modes allowed for Timer 0 and Timer 1.
相關(guān)PDF資料
PDF描述
71M6531F-IMR/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
71M6532D-IGT/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
71M6531D-IMR/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
71M6532F-IGTR/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
71M6532D-IGT/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
71M6532F-IGTR/F 功能描述:計(jì)量片上系統(tǒng) - SoC Residential Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時(shí)鐘頻率:70 Hz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數(shù)量:12 片上 ADC: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel
71M6532F-IGTR/F1 功能描述:計(jì)量片上系統(tǒng) - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時(shí)鐘頻率:70 Hz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數(shù)量:12 片上 ADC: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel
71M6533 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Energy Meter IC
71M6533-DB 功能描述:開(kāi)發(fā)板和工具包 - 8051 71M6533 Demo Brd RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評(píng)估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓:
71M6533G 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Exceeds IEC 62053/ANSI C12.20 Standards