參數(shù)資料
型號(hào)： 71M6531F-IM/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
封裝： LEAD FREE, QFN-68
文件頁(yè)數(shù)： 39/120頁(yè)
文件大?。?/td> 2477K
代理商： 71M6531F-IM/F
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FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
v1.3
2005-2010 TERIDIAN Semiconductor Corporation
25
Register
(Alternate Name)
SFR
Address
Bit Field
Name
R/W
Description
ERASE
(FLSH_ERASE)
0x94
W
This register is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle.
See the Flash Memory section for details.
FL_BANK
0xB6[2:0]
R/W
Flash Bank Selection.
PGADDR
(FLSH_PGADR[5:0])
0xB7
R/W
Flash Page Erase Address register. Contains
the flash memory page address (page 0 through
page 127) that will be erased during the Page
Erase cycle (default = 0x00).
Must be re-written for each new Page Erase
cycle.
FLSHCRL
0xB2[0]
FLSH_PWE
R/W
Program Write Enable:
0:
MOVX commands refer to XRAM
Space, normal operation (default).
1:
MOVX @DPTR,A moves A to Program
Space (Flash) @ DPTR.
0xB2[1]
FLSH_MEEN
W
Mass Erase Enable:
0:
Mass Erase disabled (default).
1:
Mass Erase enabled.
Must be re-written for each new Mass Erase
cycle.
0xB2[6]
SECURE
R/W
Enables security provisions that prevent external
reading of flash memory and CE program RAM.
This bit is reset on chip reset and may only be
set. Attempts to write zero are ignored.
0xB2[7]
PREBOOT
R
Indicates that the preboot sequence is active.
IFLAGS
0xE8[0]
IE_XFER
R/W
This flag monitors the XFER_BUSY interrupt.
It is set by hardware and must be cleared by
the interrupt handler.
0xE8[1]
IE_RTC
R/W
This flag monitors the RTC_1SEC interrupt. It
is set by the hardware and must be cleared by
the interrupt handler.
0xE8[2]
FWCOL1
R/W
This flag indicates that a flash write was in
progress while the CE was busy.
0xE8[3]
FWCOL0
R/W
This flag indicates that a flash write was
attempted when the CE was attempting to
begin a code pass.
0xE8[4]
IE_PB
R/W
This flag indicates that the wake-up pushbutton
was pressed.
0xE8[5]
IE_WAKE
R/W
This flag indicates that the MPU was awakened
by the autowake timer.
0xE8[6]
PLL_RISE
R/W
PLL_RISE Interrupt Flag:
Write 0 to clear the PLL_RISE interrupt flag.
0xE8[7]
PLL_FALL
R/W
PLL_FALL Interrupt Flag:
Write 0 to clear the PLL_FALL interrupt flag.
INTBITS
(INT0 … INT6)
0xF8[6:0]
INT6 … INT0
R
Interrupt inputs. The MPU may read these bits
to see the status of external interrupts INT0 up
to INT6. These bits do not have any memory
and are primarily intended for debug use.
0xF8[7]
WD_RST
W
The WDT is reset when a 1 is written to this
bit.
Only byte operations on the entire INTBITS register should be used when
writing. The byte must have all bits set except the bits that are to be
cleared.
相關(guān)PDF資料
PDF描述
71M6532F-IGT/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
71M6531F-IMR/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
71M6532D-IGT/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
71M6531D-IMR/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
71M6532F-IGTR/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
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