參數(shù)資料
型號: 71M6511H-IGT
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64
封裝: LQFP-64
文件頁數(shù): 50/98頁
文件大?。?/td> 1278K
代理商: 71M6511H-IGT
71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
NOVEMBER 2010
Page: 54 of 98
2005–2010 Teridian Semiconductor Corporation
V2.7
A Maxim Integrated Products Brand
Accumulation Interval m
MUX
cycle n
MUX
cycle 2
MUX
cycle 3
Chop Polarity
Positive
Re-
versed
Re-
versed
Re-
versed
Re-
versed
MUX
cycle n
MUX
cycle 1
MUX
cycle 1
MUX
cycle 1
Accumulation Interval m+1
CE_BUSY interrupt
(falling edge)
XFER_BUSY interrupt
(falling edge)
Accumulation Interval m+2
Positive
Re-
versed
Figure 21: Chop Polarity w/ Automatic Chopping
If temperature compensation or accurate reading of the die temperature is required, alternate multiplexer cycles have to be
inserted in between the regular cycles. This is done under MPU firmware control by asserting the MUX_ALT bit whenever
necessary. Since die temperature usually changes very slowly, alternate multiplexer cycles have to be inserted very
infrequently. Usually, an alternate multiplexer cycle is inserted once for every accumulation period, i.e. after each
XFER_BUSY interrupt. This sequence is shown in Figure 22.
Accumulation Interval m
MUX
cycle n
MUX
cycle 2
MUX
cycle 3
Chop Polarity
Positive
Re-
versed
Re-
versed
Re-
versed
Re-
versed
MUX
cycle n
Accumulation Interval m+1
alt. MUX
cycle
alt. MUX
cycle
alt. MUX
cycle
CE_BUSY interrupt
XFER_BUSY interrupt
Accumulation Interval m+2
Positive
Re-
versed
MUX_ALT
Figure 22: Sequence with Alternate Multiplexer Cycles
This sequence has the disadvantage that the alternate multiplexer cycle is always operated with positive connection.
Consequently, DC offset will appear on the temperature measurement, which will decrease the accuracy of this measurement
and thus cause temperature reading and compensation to be less accurate.
The sequence shown in Figure 23 uses the CHOP_EN bits to control the chopper polarity after each XFER_BUSY interrupt.
CHOP_EN is controlled to alternate between 10 (positive) and 01 (reversed) for the first multiplexer cycle following each
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