參數資料
型號: 7140LA55CGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 1K X 8 DUAL-PORT SRAM, 55 ns, CDIP48
封裝: 0.620 X 2.430 INCH, 0.150 INCH HEIGHT, GREEN, SIDE BRAZED, DIP-48
文件頁數: 6/19頁
文件大小: 149K
代理商: 7140LA55CGI
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
14
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(2)
NOTES:
1.
PLCC, TQFP and STQFP package only.
2.
'X' in part numbers indicates power rating (SA or LA).
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
Timing Waveform by BUSY Arbitration Controlled
by Address Match Timing(1)
tAPS
ADDR
'A'
AND 'B'
ADDRESSES MATCH
tBAC
tBDC
CE'B'
CE'A'
BUSY'A'
2689 drw 14
(2)
BUSY'B'
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
tAPS
ADDR'A'
ADDR'B'
2689 drw 15
(2)
tBAA
tBDA
tRC OR tWC
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the
BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7130 only).
7130X20(1)
7140X20(1)
Com'l Only
7130X25
7140X25
Com'l, Ind
& Military
7130X35
7140X35
Com'l
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tINS
Interrupt Set Time
____
20
____
25
____
25
ns
tINR
Interrupt Reset Time
____
20
____
25
____
25
ns
2689 tbl 12a
相關PDF資料
PDF描述
7140SA25PFGI 1K X 8 DUAL-PORT SRAM, 25 ns, PQFP64
7140LA25JGI 1K X 8 DUAL-PORT SRAM, 25 ns, PQCC52
IDT7140SA25PFGB HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
IDT7140SA25PFGI HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
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