參數(shù)資料
型號: 7140LA25PFG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 1K X 8 DUAL-PORT SRAM, 25 ns, PQFP64
封裝: 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-64
文件頁數(shù): 19/19頁
文件大小: 149K
代理商: 7140LA25PFG
9
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 2, Either Side(3)
NOTES:
1. Timing depends on which signal is asserted last,
OE or CE.
2. Timing depends on which signal is deaserted first,
OE or CE.
3. R/
W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW.
4.
Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 1, Either Side(1)
ADDRESS
DATAOUT
tRC
tOH
PREVIOUS DATA VALID
tAA
tOH
DATA VALID
2689 drw 08
tBDDH
(2,3)
BUSYOUT
NOTES:
1. R/
W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations,
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
CE
tACE
tAOE
tHZ
tLZ
tPD
VALID DATA
tPU
50%
OE
DATAOUT
CURRENT
ICC
ISS
50%
2689 drw 09
(4)
(1)
(2)
(4)
tLZ
tHZ
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