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參數(shù)資料
| 型號(hào)： | 70T3399S133DD |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 18 DUAL-PORT SRAM, 15 ns, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144 |
| 文件頁(yè)數(shù)： | 16/28頁(yè) |
| 文件大?。?/td> | 429K |
| 代理商： | 70T3399S133DD |
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6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
23
Functional Description
TheIDT70T3339/19/99providesatruesynchronousDual-PortStatic
RAM interface.Registeredinputsprovideminimalset-upandholdtimes
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internalwritepulsewidthisindependentofthecycletime.
An asynchronous output enable is provided to ease asyn-
chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall
the operation of the address counters for fast interleaved
memoryapplications.
AHIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70T3339/19/99s for depth
expansion configurations. Two cycles are required with CE0 LOW and
CE1 HIGHtore-activatetheoutputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
addresslocation7FFFEwhenCEL = VIL and R/WL= VIH.Likewise,the
right port interrupt flag (INTR) is asserted when the left
port writes to memory location 7FFFF (HEX) and to clear the interrupt
flag(INTR),therightportmustreadthememorylocation7FFFF(3FFFF
or 3FFFE for IDT70T3319 and 1FFFF or 1FFFE for IDT70T3399). The
message(18bits)at7FFFEor7FFFF(3FFFFor3FFFEforIDT70T3319
and 1FFFF or 1FFFE for IDT70T3399) is user-defined since it is an
addressableSRAMlocation.Iftheinterruptfunctionisnotused,address
locations 7FFFE and 7FFFF (3FFFF or 3FFFE for IDT70T3319 and
1FFFF or 1FFFE for IDT70T3399) are not used as mail boxes, but as
partoftherandomaccessmemory.RefertoTruthTableIII fortheinterrupt
operation.
Collision Detection
Sleep Mode
The IDT70T3339/19/99 is equipped with an optional sleep or low
power mode on both ports. The sleep mode pin on both ports is
asynchronous and active high. During normal operation, the ZZ pin is
pulledlow.WhenZZispulledhigh,theportwillentersleepmodewhere
it will meet lowest possible power conditions. The sleep mode timing
diagramshowsthemodes ofoperation:NormalOperation,NoRead/Write
Allowed and Sleep Mode.
Fornormaloperationallinputsmustmeetsetupandholdtimesprior
tosleepand afterrecoveringfromsleep.Clocksmustalsomeetcyclehigh
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx=VIH)andthreecyclesafterde-assertingZZ(ZZx=VIL),thedevice
mustbedisabledviathechipenablepins.Ifawriteorreadoperationoccurs
duringtheseperiods,thememoryarraymaybecorrupted.Validityofdata
outfromtheRAMcannotbeguaranteedimmediatelyafterZZisasserted
(priortobeinginsleep).Whenexitingsleepmode,thedevicemustbein
Read mode (R/Wx = VIH)when chip enable is asserted, and the chip
enablemustbevalidforonefullcyclebeforeareadwillresultintheoutput
of valid data.
DuringsleepmodetheRAMautomaticallydeselectsitself.TheRAM
disconnectsitsinternalclockbuffer.Theexternalclockmaycontinuetorun
withoutimpactingtheRAMssleepcurrent(IZZ).Alloutputswillremainin
high-Zstatewhileinsleepmode.Allinputsareallowedtotoggle.TheRAM
will not be selected and will not perform any reads or writes.
Collision is defined as an overlap in access between the two ports
resulting in the potential for either reading or writing incorrect data to a
specific address. For the specific cases: (a) Both ports reading - no
dataiscorrupted,lost,orincorrectlyoutput,sonocollisionflagisoutput
on either port. (b) One port writing, the other port reading - the end
result of the write will still be valid. However, the reading port might
capture data that is in a state of transition and hence the reading port’s
collision flag is output. (c) Both ports writing - there is a risk that the two
ports will interfere with each other, and the data stored in memory will
not be a valid write from either port (it may essentially be a random
combinationofthetwo). Therefore,thecollisionflagisoutputonboth
ports. Please refer to Truth Table IV for all of the above cases.
The alert flag (COL
X) is asserted on the 2nd or 3rd rising clock
edgeoftheaffectedportfollowingthecollision,andremainslowfor
one cycle. Please refer to Collision DetectionTiming table on Page 21.
During that next cycle, the internal arbitration is engaged in resetting
the alert flag (this avoids a specific requirement on the part of the user
to reset the alert flag). If two collisions occur on subsequent clock
cycles,thesecondcollisionmaynotgeneratetheappropriatealert
Collision detection on the IDT70T3339/19/99 represents a
significantadvanceinfunctionalityovercurrentsyncmulti-ports,which
havenosuchcapability. Inadditiontothisfunctionalitythe
IDT70T3339/19/99 sustains the key features of bandwidth and
flexibility. Thecollisiondetectionfunctionisveryusefulinthecaseof
bursting data, or a string of accesses made to sequential addresses, in
thatitindicatesaproblemwithintheburst,givingtheusertheoptionof
either repeating the burst or continuing to watch the alert flag to see
whetherthenumberofcollisionsincreasesaboveanacceptable
thresholdvalue.Offeringthisfunctiononchipalsoallowsusersto
reduce their need for arbitration circuits, typically done in CPLD’s or
FPGA’s. This reduces board space and design complexity, and gives
the user more flexibility in developing a solution.
flag. A third collision will generate the alert flag as appropriate. In the
event that a user initiates a burst access on both ports with the same
starting address on both ports and one or both ports writing during
eachaccess(i.e.,imposesalongstringofcollisionsoncontiguous
clock cycles), the alert flag will be asserted and cleared every other
cycle.PleaserefertotheCollisionDetectiontimingwaveformonpage
21.
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參數(shù)描述 |
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| 70T3399S166BC | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 12ns/3.6ns 256-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 12NS/3.6NS 256BGA - Rail/Tube |
| 70T3399S166BC8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 12ns/3.6ns 256-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 12NS/3.6NS 256BGA - Tape and Reel |
| 70T3399S166BF | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 12ns/3.6ns 208-Pin FBGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 12NS/3.6NS 208FPBGA - Rail/Tube |
| 70T3399S166BF8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 12ns/3.6ns 208-Pin FBGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 12NS/3.6NS 208FPBGA - Tape and Reel |
| 70T3399S200BC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:IDT 存儲(chǔ)容量: 組織: 訪問時(shí)間: 電源電壓-最大: 電源電壓-最小: 最大工作電流: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
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