參數(shù)資料
型號(hào): 6N139-SMT&R
廠商: ISOCOM COMPONENTS LTD
元件分類: 光電耦合器
英文描述: 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 0.3 Mbps
封裝: SURFACE MOUNT PACKAGE-8
文件頁(yè)數(shù): 3/4頁(yè)
文件大?。?/td> 79K
代理商: 6N139-SMT&R
SWITCHING SPECIFICATIONS AT T
A = 25°C ( VCC = 5V Unless otherwise noted )
PARAMETER
SYM DEVICE
MIN TYP MAX UNITS TESTCONDITION
Propagation Delay Time
6N139
5.0
25
s
I
F = 0.5mA,RL = 4.7k
to Logic Low at Output
t
PHL
6N139
0.2
1
s
I
F = 12mA,RL = 270
( fig 1 )( note6,8 )
6N138
1.0
10
s
I
F = 1.6mA,RL = 2.2k
Propagation Delay Time
6N139
1.0
60
s
I
F = 0.5mA,RL = 4.7k
to Logic High at Output
t
PLH
6N139
1.0
7
s
I
F = 12mA,RL = 270
( fig 1 )( note6,8 )
6N138
4.0
35
s
I
F = 1.6mA,RL = 2.2k
Common Mode Transient
Immunity at Logic High
CM
H
1000 10000
V/
s
I
F = 0mA, VCM = 10VPP
Level Output ( fig 2 )( note9 )
R
L = 2.2k
Common Mode Transient
Immunity at Logic Low
CM
L
1000
10000
V/
s
I
F= 1.6mA,VCM= 10VPP
Level Output ( fig 2 )( note9 )
R
L = 2.2k
NOTES:-
1.
Derate linearly above 50oC free air temperature at a rate of 0.4 mA/°C.
2.
Derate linearly above 50oC free air temperature at a rate of 0.7 mW/°C.
3.
Derate linearly above 25oC free air temperature at a rate of 0.7 mA/°C.
4.
Derate linearly above 25oC free air temperature at a rate of 2.0 mW/°C.
5.
CURRENT TRANSFER RATIO is defined as the ratio of output collector current,I
O , to the forward LED
input current, I
F multiplied by 100%.
6.
Pin 7 open.
7.
Device considered a two-terminal device: pins 1,2,3, and 4 shorted together and pins 5,6,7 and 8 shorted
together.
8.
Use of a resistor between pin 5 and 7 will decrease gain and delay time.
9.
Common mode transient immunity in Logic High level is the maximum tolerable (positive) dVcm/dt on
the leading edge of the common mode pulse V
CM to assure that the output will remain in a Logic High
state (i.e. V
O > 2.0V). Common mode transient immunity in Logic Low level is the maximum tolerable
(negative) dVcm/dt on the trailing edge of the common mode pulse signal, V
CM to assure that the output
will remain in Logic Low state (i.e. V
O< 0.8V).
FIG.1 SWITCHING TEST CIRCUIT
2
I
F Monitor
0
I
F
V
O
1.5V
100
1.5V
5V
t
PHL
t
PLH
V
OL
R
L
V
O
C
L = 15pF
8
7
6
5
PULSE
GENERATOR
Z
O = 50
t
r = 5ns
I
F
1
4
3
10% Duty Cycle
1/f < 100
s
5V
DB91037-AAS/A3
22/5/03
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