Advance Information
MC68HC908MR16/MC68HC908MR32
—
Rev. 5.0
24
List of Figures
MOTOROLA
List of Figures
Figure
Title
Page
11-5
11-6
TIMA Counter Registers (TACNTH and TACNTL). . . . . . .216
TIMA Counter Modulo Registers
(TAMODH and TAMODL) . . . . . . . . . . . . . . . . . . . . . . .217
TIMA Channel Status
and Control Registers (TASC0
–
TASC3). . . . . . . . . . . .218
CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
TIMA Channel Registers (TACH0H/L
–
TACH3H/L) . . . . . .222
11-7
11-8
11-9
12-1
12-2
12-3
12-4
12-5
12-6
TIMB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
TIMB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .228
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . .232
TIMB Status and Control Register (TBSC). . . . . . . . . . . . .238
TIMB Counter Registers (TBCNTH and TBCNTL). . . . . . .240
TIMB Counter Modulo Registers
(TBMODH and TBMODL) . . . . . . . . . . . . . . . . . . . . . . .241
TIMB Channel Status
and Control Registers (TBSC0
–
TBSC1). . . . . . . . . . . .242
CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
TIMB Channel Registers (TBCH0H/L
–
TBCH1H/L) . . . . . .246
12-7
12-8
12-9
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .252
SPI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .253
Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . .253
Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . .256
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . .257
Transmission Start Delay (Master). . . . . . . . . . . . . . . . . . .259
Missed Read of Overflow Condition. . . . . . . . . . . . . . . . . .261
Clearing SPRF When OVRF Interrupt Is Not Enabled. . . .262
SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . .265
SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . .267
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . .272
SPI Status and Control Register (SPSCR). . . . . . . . . . . . .274
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . .277
14-1
14-2
SCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .281
SCI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .282