Pinout and Signal Descriptions
Signal Descriptions
68HC(9)12DG128 Rev 1.0
MOTOROLA
Pinout and Signal Descriptions
37
13-pins
ECLK
PE7
36
Inverted E clock used to latch the address.
CAL is the output of the Slow Mode programmable clock divider, SLWCLK,
and is used as a calibration reference for functions such as time of day. It is
overridden when DBE function is enabled. It always has a 50% duty.
Clock generation module test output.
State of mode select pins during reset determine the initial operating mode
of the MCU. After reset, MODB and MODA can be configured as
instruction queue tracking signals IPIPE1 and IPIPE0 or as
general-purpose I/O pins.
E Clock is the output connection for the external bus clock. ECLK is used
as a timing reference and for address demultiplexing.
Low byte strobe (0 = low byte valid), in all modes this pin can be used as
I/O. The low strobe function is the exclusive-NOR of A0 and the internal
SZ8 signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin
function TAGLO used in instruction tagging. See
Development Support
.
Indicates direction of data on expansion bus. Shares function with
general-purpose I/O. Read/write in expanded modes.
Maskable interrupt request input provides a means of applying
asynchronous interrupt requests to the MCU. Either falling edge-sensitive
triggering or level-sensitive triggering is program selectable (INTCR
register).
Provides a means of requesting asynchronous nonmaskable interrupt
requests after reset initialization
During reset, this pin determines special or normal operating mode. After
reset, single-wire background interface pin is dedicated to the background
debug function. Pin function TAGHI used in instruction tagging. See
Development Support
.
Page Index register emulation outputs.
Emulation Chip select.
Pulse Width Modulator channel outputs.
Slave select output for SPI master mode, input for slave mode or master
mode.
Serial clock for SPI system.
Master out/slave in pin for serial peripheral interface
Master in/slave out pin for serial peripheral interface
SCI1 transmit pin
SCI1 receive pin
SCI0 transmit pin
SCI0 receive pin
CAL
PE7
36
CGMTST
MODB/IPIPE
1,
MODA/IPIPE
0
PE6
37
PE6, PE5
37, 38
ECLK
PE4
39
LSTRB/TAGL
O
PE3
53
R/W
PE2
54
IRQ
PE1
55
XIRQ
PE0
56
SMODN/BKG
D/TAGHI
-
23
IX[2:0]
ECS
PW[3:0]
PK[2:0]
PK7
PP[3:0]
109-111
108
112, 1–3
SS
PS7
96
SCK
PS6
PS5
PS4
PS3
PS2
PS1
PS0
95
94
93
92
91
90
89
SDO/MOSI
SDI/MISO
TxD1
RxD1
TxD0
RxD0
Table 7 XC68HC912D60 Signal Description Summary
Pin Name
Shared
port
Pin
Number
112-pin
Description