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參數(shù)資料
| 型號： | 62256 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 158K |
| 代理商： | 62256 |
Revision 4.0
December 1997
KM62256C Family
CMOS SRAM
5
C
L
1)
1. Including scope and jig capacitance
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falingl time : 5ns
input and output reference voltage : 1.5V
Output load (See right) :C
L
=100pF+1TTL
AC OPERATING CONDITIONS
A
C CHARACTERISTICS
(Vcc=4.5~5.5V, KM62256C Family : T
A
=0 to 70
°
C, KM62256CE Family : T
A
=-25 to 85
°
C,
KM62256CI Family : T
A
=-40 to 85
°
C)
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
ns
Address access time
t
AA
-
55
-
70
ns
Chip select to output
t
CO
-
55
-
70
ns
Output enable to valid output
t
OE
-
25
-
35
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
20
0
30
ns
Output disable to high-Z output
t
OHZ
0
20
0
30
ns
Output hold from address change
t
OH
5
-
5
-
ns
Write
Write cycle time
t
WC
55
-
70
-
ns
Chip select to end of write
t
CW
45
-
60
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
ns
Write pulse width
t
WP
40
-
50
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
25
ns
Data to write time overlap
t
DW
25
-
30
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
-
Max
Unit
Vcc for data retention
V
DR
CS
≥
Vcc-0.2V
2.0
5.5
V
Data retention current
I
DR
KM62256CL
KM62256CL-L
KM62256CLE
KM62256CLE-L
KM62256CLI
KM62256CLI-L
Vcc=3.0V
CS
≥
Vcc-0.2V
L-Ver
LL-Ver
L-Ver
LL-Ver
L-Ver
LL-Ver
-
-
-
-
-
-
0
1
0.5
-
-
-
-
-
50
10
50
25
50
25
-
μ
A
Data retention set-up time
t
SDR
See data retention waveform
ms
Recovery time
t
RDR
5
-
-
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