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參數(shù)資料
| 型號(hào)： | 603J500821MXTE03 |
| 廠商： | SYFER TECHNOLOGY LTD |
| 元件分類： | 數(shù)據(jù)傳輸濾波器 |
| 英文描述： | 1 FUNCTIONS, 50 V, FEED THROUGH CAPACITOR |
| 封裝： | EIA STD PACKAGE SIZE 0603, CERAMIC PACKAGE-3 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大小： | 194K |
| 代理商： | 603J500821MXTE03 |
Ordering Information
1206
Chip Size
Reference
J
Termination
J = Nickel
Barrier
100
Voltage
016 = 16 volts
025 = 25 volts
050 = 50 volts
100 = 100 volts
0222
Capacitance
Expressed in picofarads (pF).
First digit is 0.
Second and third digits are significant
figures of capacitance code.
The fourth digit is number of zeros
following.
Example: 0222=2200pF.
M
Tolerance
M= ±20%
X
Dielectric
C = C0G
X = X7R
T
Packaging
T =178mm
(7”) reel
R =330mm
(13”) reel
B=Bulk
E03
Balanced Line
EMI Chip
Integrated Passive Components
Balanced Line EMI Chip
BLC
Application Note
One of the significant features of this product is its extremely low
inductance, making it particularly suitable for high speed digital
applications and for reduction of common mode currents for power
line applications. Inductance cancellation, due to the effect of
opposing current flow across the device, results in a typical line to
line inductance of around 100pH, with a corresponding line to
ground inductance of 50pH.
The Balanced Line EMI chip satisfies the need for high speed
communications systems using balanced lines or twisted pairs
offering low inductance (therefore high frequency operation),
reduced board space, reduced component count and an
unparalleled performance.
●
Syfer Technology are able to provide comprehensive applications
and design in support.
●
Technical and application papers are available on request from
the Sales Office.
Manufactured in the UK by Syfer Technology Limited under licence from X2Y attenuators LLC.
62
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