VERSACLOCK LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
參數(shù)資料
型號(hào): 5P49EE602NLGI
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 8/26頁(yè)
文件大小: 0K
描述: IC CLOCK GENERATOR 24QFN
標(biāo)準(zhǔn)包裝: 75
系列: VersaClock™
類型: 時(shí)鐘發(fā)生器
PLL: 帶旁路
輸入: LVTTL,晶體
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 無/是
頻率 - 最大: 120MHz
除法器/乘法器: 是/無
電源電壓: 1.71 V ~ 1.89 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 管件
其它名稱: 800-2525
IDT5P49EE602
VERSACLOCK LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
IDT VERSACLOCK LOW POWER CLOCK GENERATOR
16
IDT5P49EE602
REV L 072512
AC Timing Electrical Characteristics
(Spread Spectrum Generation = OFF)
1) Input clock (square wave) may be used at 1 MHz.
2) Time from supply voltage crosses VDD=1.62V to PLLs are locked.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
fIN
Input Frequency
Input Frequency Limit (CLKIN)
11
40
MHz
1 / t1
Output Frequency
Single Ended Clock output limit (LVTTL) 3.3V
0.001
120
MHz
Single Ended Clock output limit (LVTTL) 2.5V
110
MHz
Single Ended Clock output limit (LVTTL) 1.8V
100
MHz
fVCO
VCO Frequency
VCO operating Frequency Range
100
475
MHz
fPFD
PFD Frequency
PFD operating Frequency Range
0.300 1
20
MHz
t2
Input Duty Cycle
Duty Cycle for Input
40
60
%
t3
Output Duty Cycle
Measured at VDD/2
45
55
%
t4
Slew Rate, SLEWx(bits) = 00
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
5.1
V/ns
Slew Rate, SLEWx(bits) = 01
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
4.4
Slew Rate, SLEWx(bits) = 10
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
2.8
Slew Rate, SLEWx(bits) = 11
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
1.8
t5
Clock Jitter
Peak-to-peak period jitter, CLK outputs
measured at VDD/2; fPFD >= 10 MHz
Single output frequency only.
100
ps
Peak-to-peak period jitter, CLK outputs
measured at VDD/2; fPFD >= 10 MHz
Multiple output frequencies switching.
200
ps
t6
Output Skew
Skew between output to output on the same
bank
75
ps
Skew between any output (Same freq and IO
type, FOUT >10MHz)
200
ps
t7
Lock Time
PLL Lock Time from Power-up (using MHz
reference clock)2
520
ms
PLL Lock Time from Power-up using
32.768kHz reference clock)
13
s
PLL Lock time from shutdown mode
5
10
ms
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5P49EE801NDGI 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 VERSACLOCK LOW POWER PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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