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| 型號(hào)： | 5D12.185B |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 89K |
| 代理商： | 5D12.185B |
A
1 Watt SLC Dual Series DC/DC Converters
2401 Stanwell Drive Concord, California 94520 Ph: 925/687-4411 or 800/542-3355 Fax: 925/687-3333 www.calex.com Email: sales@calex.com
3
3/2001
Mechanical tolerances unless otherwise noted:
X.XX dimensions: ±0.020 inches
X.XXX dimensions: ±0.010 inches
Operation With Changing Input Voltage
The output will change proportionally to a change in the input
voltage. The typical output voltage change is 1.2% per 1%
change in input voltage.
Low Noise Output Circuit
The circuit shown in Figure 3 can be used to reduce the output
noise to below 8 mV p-p over a 20 MHz bandwidth. Size
inductor L2 appropriately for the maximum expected load
current. All the ground connections must be as short as
possible back to the CMN pin. The filter should be placed as
close as possible to the converter, even if your load is at some
distance.
Single Ended Loads
The SLC Dual series may be operated in a single ended mode
to get 10, 14, 24, 28, 30 or 34 volt outputs. The circuit of Figure
4 should be used for single ended operation. The CMN pin
should be left floating from your application ground.
Output Short Circuit Protection
This series is only protected for momentary output short
circuits to common so a fast acting fuse or input current
limiting is recommended to protect the converter. If output
shorts are possible then the protection circuit should not be
omitted as it serves to prevent unlimited current from flowing
in the case of an overcurrent at the load.
Very Low Noise Input Circuit
Figure 2 shows a very low noise input circuit that may be used
with the converters. This circuit will reduce the input reflected
ripple current to less than 10 mA peak to peak. L1 should be
sized to handle the maximum DC current of your application.
C1 must be used if L1 is required in the circuit.
Figure 2.
This circuit will reduce the input reflected ripple current to less than
10 mA peak to peak. See the discussion in the text for selecting C1
and L1.
Applying The Output
Figure 1 shows the typical output connection for the converter.
C2 is required for proper operation of the outputs. C2 should
be at least 2.2μF minimum and can be made up of the bypass
capacitors already used in your application. A low ESR 10μF
Tantalum capacitor is recommended. Decreasing the ESR of
C2 will lower the output noise.
Operation With Light Loads
This converter uses a semi-regulated design. The output
voltage will vary as the load is changed, increasing as the load
is decreased. See the Output Voltage vs. Output Load curve
for more information.
Figure 3.
This circuit can reduce the output noise to below 8mV P-P over a 20
MHz bandwidth. Size L2 for the maximum expected load current.
Place as close as possible to the converter.
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C2, C3 = . 2.2 μF, 10 μF TYPICAL
L2 = 1 μH-5 μH
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