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參數(shù)資料
| 型號： | 5962R8958702VXA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 固定正電壓單路輸出LDO穩(wěn)壓器 |
| 英文描述： | 5 V FIXED POSITIVE LDO REGULATOR, 1 V DROPOUT, CDSO16 |
| 封裝： | CERAMIC, SOIC-16 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大小： | 410K |
| 代理商： | 5962R8958702VXA |
AC Parameters
SMD: 5962R8958702
The following conditions apply, unless otherwise specified.
AC:
V
I = 10V, IO = 1A, CO = 22F
Symbol
Parameter
Conditions
Notes
Min
Max
Unit
Sub-
groups
Max Line Transient
V
O ≤ 6V, RO = 100, t = 20mS
40
V
1, 2, 3
Reverse Polarity Input Voltage
Transient
t = 20mS, R
O = 100
-45
V
1, 2, 3
RR
Ripple Rejection
V
IN = 10V, 1VRMS, = 1KHz,
I
OUT = 5mA
60
dB
4
50
dB
5, 6
N
O
Output Noise Voltage
V
IN = 10V, IOUT = 5mA,
10Hz - 100KHz
0.0
700
V
RMS
1, 2, 3
Z
O
Output Impedance
V
IN = 10V, O = 120Hz
I
OUT = 100mA DC and 20mA AC
1.0
1, 2, 3
DC Drift Parameters
The following conditions apply, unless otherwise specified.
DC:
V
I = 10V, IO = 1A, CO = 22F, “Delta calculations performed on QMLV devices at group B, subgroup 5 only”
Symbol
Parameter
Conditions
Notes
Min
Max
Unit
Sub-
groups
V
O
Output Voltage
V
IN = 10V, IOUT = 5mA
-30
30
mV
1
V
IN = 6V, IOUT = 5mA
-30
30
mV
1
V
IN = 7V, IOUT = 5mA
-30
30
mV
1
V
IN = 26V, IOUT = 5mA
-30
30
mV
1
V
IN = 10V, IOUT = 1A
-30
30
mV
1
V
IN = 6V, IOUT = 1A
-30
30
mV
1
V
IN = 6V, IOUT = 50mA
-30
30
mV
1
V
IN = 10V, IOUT = 50mA
-30
30
mV
1
V
RLOAD
Load Regulation
V
IN = 10V, 50mA ≤ IOUT ≤ 1A
-20
20
mV
1
Note 2:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 3:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax (maximum junction temperature), θJA (package
junction to ambient thermal resistance), and T
A (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/
θ
JA or the number given in the Absolute Maximum Ratings, whichever is lower. With heat sinking, the maximum power is 5 Watts, but then this will depend upon
the temperature of the heat sink, the efficiency of the heat sink, and the efficiency of the heat flow between the package body and the heat sink. We can not
predict these values.
Note 4:
The package material for these devices allows much improved heat transfer over our standard ceramic packages. In order to take full advantage of this
improved heat transfer, heat sinking must be provided between the package base (directly beneath the die), and either metal traces on, or thermal vias through,
the printed circuit board. Without this additional heat sinking, device power dissipation must be calculated using
θ
JA, rather than θJC, thermal resistance. It must
not be assumed that the device leads will provide substantial heat transfer out of the package, since the thermal resistance of the lead frame material is very
poor, relative to the material of the package base. The stated
θ
JC thermal resistance is for the package material only, and does not account for the additional
thermal resistance between the package base and the printed circuit board. The user must determine the value of the additional thermal resistance and must
combine this with the stated value for the package, to calculate the total allowed power dissipation for the device.
Note 5:
Human body model, 1.5 k
Ω in series with 100 pF.
Note 6:
Functional test only.
Note 7:
These parts are tested on a wafer by wafer basis at high and low dose rates according to MIL-STD-883 Test Method 1019 Conditions A and D with no
enhanced low dose rate sensitivity (ELDRS). Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics.
7
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LM2940QML
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