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參數(shù)資料
| 型號： | 5962R0521403QXX |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, CDFP48 |
| 封裝： | CERAMIC, DFP-48 |
| 文件頁數(shù)： | 21/22頁 |
| 文件大小： | 174K |
| 代理商： | 5962R0521403QXX |
8
3sOE
ILVTTL
Synchronous Output Enable.
The sOE input is used to synchronously enable/
disable the output clocks. Each clock output that is controlled by the sOE pin is
synchronously enabled/disabled by the individual output clock. When HIGH, sOE
disables all clocks except 2Q0 and 2Q1. When disabled, 1Q0, 1Q1, 3Q0, and 3Q1
will always enter a LOW state when PE/HD is MID or HIGH, and they will disable
into a HIGH state when PE/HD is LOW.
The disabled state of 4Q0 and 4Q1 is dependent upon the state of PE/HD and 4F[1:0].
The following table illustrates the disabled state of bank 4 outputs as they are
controlled by the state of PE/HD and 4F[1:0].
PE/HD
4F[1:0]*
4Q0
4Q1
LOW
HH
LOW
MID
HH
HIGH
HH
HIGH
*All other combinations of 4F[1:0] will result in 4Q0 and 4Q1 disabling into
a LOW state when PE/HD is MID or HIGH, and they will disable into a
HIGH
state when PE/HD is LOW.
When TEST is held at the MID level and sOE is HIGH, the nF[1:0] pins act as
individual output enable/disable controls for each output bank, excluding bank 2.
Setting both nF[1:0] signals LOW disables the corresponding output bank.
Set sOE LOW to place the UT7R995/C RadClockTM outputs into their normal
operating modes.
1, 2, 24,
25, 26, 27,
47, 48
nF[1:0]
I
3-Level
Output divider and phase skew selection for each output bank.
Please see Tables 3, 4, 5, 6, and 9 for a complete explanation of the nF[1:0] control
functions and their effects on output frequency and skew.
46
FS
I
3-Level
VCO operating frequency range selection.
Please see Tables 7 and 8.
8, 9, 17,
18, 31, 32,
41, 42
nQ[1:0]
O
LVTTL
Four clock banks of two outputs each.
Please see Table 6 for frequency settings and Table 9 for skew settings.
22, 23
DS[1:0]
I
3-Level
Feedback input divider selection.
Please see Table 1 for a summary of the feedback input divider settings.
5
PE/HD
I
3-Level
Positive/negative edge control and high/low output drive strength selection.
The
PE portion of this pin controls which edge of the reference input synchronizes the
clock outputs. The HD portion of this pin controls the drive strength of the output
clock buffers. The following table summarizes the effects of the PE/HD pin during
normal operation.
PE/HD
Synchronization
Output Drive Strength
LOW
Negative Edge
Low Drive
MID
Positive Edge
High Drive
HIGH
Positive Edge
Low Drive
Low drive strength outputs provide 12mA of drive strength while the high drive
condition results in 24mA of current drive. Output banks operating from a 2.5V
power supply guarantee a high drive of 20mA.
Flatpack
Pin No.
Name
I/O
Type
Description
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| 5962R0722902VXA | 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| 5962R0722961VXA | 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
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