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參數(shù)資料
| 型號： | 5962R0521402QXX |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, CDFP48 |
| 封裝： | CERAMIC, DFP-48 |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 174K |
| 代理商： | 5962R0521402QXX |
13
IN
DEVELOPMENT
9.0 AC OUTPUT ELECTRICAL CHARACTERISTICS (Pre- and Post-Radiation)*
(VDD = +3.3V + 0.3V; TC = -55°C to +125°C) (Note 1)
Symbol
Description
Condition
Min.
Max.
Unit
fOR
Output frequency range
VDDQn = +3.3V
6
200
MHz
VCOLR
VCO lock range
VDDQn = +3.3V
24
200
MHz
VCOLBW
2
VCO loop bandwidth
VDD = VDDQn = +3.3V; TC = Room Temperature
0.25
3.5
MHz
tSKEWPR
3
Matched-pair skew
Skew between the earliest and the latest output transitions
within the same bank.
--
100
ps
tSKEW0
3
Output-output skew
Skew between the earliest and the latest output transitions
among all outputs at 0tU.
--
200
ps
tSKEW1
3
Skew between the earliest and the latest output transitions
among all outputs for which the same phase delay has been
selected.
--
200
ps
tSKEW2
3
Skew between the nominal output rising edge to the
inverted output falling edge
--
500
ps
tSKEW3
3
Skew between non-inverted outputs running at different
frequencies.
--
500
ps
tSKEW4
3
Skew between nominal to inverted outputs running at
different frequencies.
--
500
ps
tSKEW5
3
Skew between nominal outputs at different power supply
levels.
--
650
ps
tPART
8
Part-part skew
Skew between the outputs of any two devices under
identical settings and conditions (VDDQn, VDD, temp, air
flow, frequency, etc).
--
750
ps
8.0 AC INPUT ELECTRICAL CHARACTERISTICS (Pre- and Post-Radiation)*
(VDD = +3.3V + 0.3V; TC = -55°C to +125°C) (VDDQn = +3.3V nominal unless otherwise noted) (Note 1)
Notes:
* Post-radiation performance guaranteed at 25
°C per MIL-STD-883 Method 1019.
1. Reference Figure 11 for clock output loading circuit that is equivalent to the load circuit used for all AC testing.
2. Supplied only as a design guideline, neither tested nor guaranteed.
3. When driving the UT7R995C with a crystal, the XTAL1 pin does not define maximum input rise/fall time.
4. Although the input reference frequencies are defined as-low-as 2MHz, the N and R dividers must be selected to ensure the PLL operates from 24MHz-50MHz when
FS = LOW, 48MHz-100MHz when FS = MID, and 96MHz-200MHz when FS = HIGH.
Symbol
Description
Condition
Min.
Max.
Unit
tR, tF
2, 3
Input rise/fall time
VIH(min)-VIL(max)
--
20
ns/V
tPWC
Input clock pulse
HIGH or LOW
2
--
ns
tXTAL
Input clock period
1÷FXTAL
5
500
ns
tDCIN
Input clock duty cycle
HIGH or LOW
10
90
%
fXTAL
4
Reference input
frequency
FS = LOW; PD/DIV = HIGH
2
50
MHz
FS = LOW; PD/DIV = MID
4
100
MHz
FS = MID; PD/DIV = HIGH
4
100
MHz
FS = MID; PD/DIV = MID
8
200
MHz
FS = HIGH; PD/DIV = HIGH
8
200
MHz
FS = HIGH; PD/DIV = MID
16
200
MHz
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