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參數(shù)資料
| 型號： | 5962H9675301VCA |
| 元件分類： | 時鐘及定時 |
| 英文描述： | ACT SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CDIP14 |
| 封裝： | CERAMIC, SIDE-BRAZED, DIP-14 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 242K |
| 代理商： | 5962H9675301VCA |
2
PIN DESCRIPTION
FUNCTIONAL TIMING: Single S
μMMIT Wait-State
For both read and write memory cycles, DTACK is an input to the S
μMMIT E and SμMMIT LXE/DXE. A non-wait state memory
requires two clock cycles, T1 and T2 of figure 1. For accessing slower memory devices, the UT54ACTS220 holds DTACK to a log-
ical “1”. This results in the stretching of memory cycles by one clock to three clock cycles, TW of figure 1. The SμMMIT E and
S
μMMIT LXE/DXE samples the DTACK on the rising edge of the 24 MHz clock. If DTACK is not generated before the rising
edge of the clock, the S
μMMIT E and SμMMIT LXE/DXE extends the memory cycle.
Pin Number
Pin Name
Description
2
CLKOUT
Buffered version of CLKIN.
3
CLKOUT
Inverted version of CLKIN.
4
CLKIN
Clock Input. This signal can be any arbitrary signal that the user wishes to buffer.
6
48MHz
48MHz Clock. The 24MHz clock is created by dividing this signal by two.
8
DMACK
DMA Acknowledge. This input is generated by the S
μMMIT. When high, this signal will
cause DTACK output to be forced high.
9
RCS
RAM Chip Select. This input is generated by the S
μMMIT.
10
MRST
Master Reset. This input can be used to preset 24MHz, DTACK and TEST. For normal
operation tie MRST to VDD through a resistor.
11
TEST
Test output signal.
12
DTACK
Data Transfer Acknowledge. This signal can be used to drive the DTACK signal of the
S
μMMIT if the user requires one wait state during the memory transfer.
13
24MHz
24MHz Clock. This output runs at half the frequency of the 48MHz input. The falling
edge of 24MHz is the signal that latches the DTACK outputs. 24MHz is forced high
whenever MRST is low. Properly loaded, 24MHz will have a 50% duty cycle
± 5%.
48MHz
24MHz
T1
T2
DMACK
RCS
DTACK
TW
Figure 1. Functional Timing
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