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參數(shù)資料
| 型號： | 5962G9655501QXX |
| 元件分類： | 計數(shù)器 |
| 英文描述： | ACT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDFP16 |
| 封裝： | BOTTOM-BRAZED, CERAMIC, DFP-16 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 249K |
| 代理商： | 5962G9655501QXX |
1
Standard Products
UT54ACS163/UT54ACTS163
4-Bit Synchronous Counters
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
Internal look-ahead for fast counting
Carry output for n-bit cascading
Synchronous counting
Synchronously programmable
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS163 - SMD 5962-96554
UT54ACTS163 - SMD 5962-96555
DESCRIPTION
The UT54ACS163 and the UT54ACTS163 are synchronous
presettable 4-bit binary counters that feature internal carry look-
ahead logic for high-speed counting designs. Synchronous op-
eration occurs by having all flip-flops clocked simultaneously
so that the outputs change coincident with each other when in-
structed by the count-enable inputs and internal gating. A buff-
ered clock input triggers the four flip-flops on the rising (posi-
tive-going) edge of the clock input waveform.
The counters are fully programmable (i.e., they may be preset
to any number between 0 and 15). Presetting is synchronous;
applying a low level at the load input disables the counter and
causes the outputs to agree with the load data after the next clock
pulse.
The clear function is synchronous and a low level at the clear
input sets all four of the flip-flop outputs low after the next clock
pulse. This synchronous clear allows the count length to be mod-
ified by decoding the Q outputs for the maximum count desired.
The counters feature a fully independent clock circuit. Changes
at control inputs (ENP, ENT, or LOAD) that modify the operat-
ing mode have no effect on the contents of the counter until
clocking occurs. The function of the counter (whether enabled,
disabled, loading, or counting) will be dictated solely by the
conditions meeting the stable setup and hold times.
The devices are characterized over full military temperature
range of -55
°C to +125°C.
PINOUTS
16-Pin DIP
Top View
16-Lead Flatpack
Top View
LOGIC SYMBOL
1
2
3
4
5
7
6
16
15
14
13
12
10
11
CLR
CLK
A
B
C
D
ENP
VDD
RCO
QA
QB
QC
QD
ENT
8
9
VSS
LOAD
1
2
3
4
5
7
6
16
15
14
13
12
10
11
VDD
89
CLR
CLK
A
B
C
D
ENP
RCO
QA
QB
QC
QD
ENT
VSS
LOAD
(1)
CLR
(9)
LOAD
M1
5CT=0
CTRDIV 16
(10)
ENT
G3
(7)
ENP
G4
(2)
CLK
(3)
A
(4)
B
(5)
C
(6)
D
(15)
RCO
(14)
QA
(11)
QD
M2
C5/2,3,4+
(12)
QC
(13)
QB
1,5D
(1)
(2)
(4)
(8)
3CT = 15
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publi-
cation 617-12.
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