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參數(shù)資料
| 型號： | 5962G9563801VYA |
| 廠商： | Aeroflex Inc. |
| 英文描述： | Radiation-Hardened MicroController |
| 中文描述： | 抗輻射微控制器 |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 347K |
| 代理商： | 5962G9563801VYA |
3
RST:
Reset Input. A high on this input for 24 oscillator periods
while the oscillator is running resets the device. All ports and
SFRs reset to their default conditions. Internal data memory is
undefined after reset. Program execution begins within 12
oscillator periods (one machine cycle) after the RST signal is
brought low. RST contains an internal pulldown resistor to allow
implementing power-up reset with only an external capacitor.
ALE:
Address Latch Enable. The ALE output is a pulse for
latching the low byte of the address during accesses to external
memory. In normal operation, the ALE pulse is output every sixth
oscillator cycle and may be used for external timing or clocking.
However, during each access to external Data Memory (MOVX
instruction), one ALE pulse is skipped.
PSEN:
Program Store Enable. This active low signal is the read
strobe to the external program memory. PSEN activates every
sixth oscillator cycle except that two PSEN activations are
skipped during external data memory accesses.
EA:
External Access Enable. This pin should be strapped to V
SS
(Ground) for the UT69RH051.
XTAL1:
Input to the inverting oscillator amplifier.
XTAL2:
Output from the inverting oscillator amplifier.
2.1 Hardware/Software Interface
2.1.1 Memory
The UT69RH051 has a separate address space for Program and
Data Memory. Internally, the UT69RH051 contains 256 bytes
of Data Memory. It addresses up to 64Kbytes of external Data
Memory and 64Kbytes of external Program Memory.
2.1.1.1 Program Memory
There is no internal program memory in the UT69RH051. All
program memory is accessed as external through ports P0 and
P2. The EA pin must be tied to V
SS
(ground) to enable access to
external locations 0000
H
through 7FFF
H
. Following reset, the
UT69RH051 fetches the first instruction at address 0000h.
2.1.1.2 Data Memory
The UT69RH051 implements 256 bytes of internal data RAM.
The upper 128 bytes of this RAM occupy a parallel address space
to the SFRs. The CPU determines if the internal access to an
address above 7F
H
is to the upper 128 bytes of RAM or to the
SFR space by the addressing mode of the instruction. If direct
addressing is used, the access is to the SFR space. If indirect
addressing is used, the access is to the internal RAM. Stack
operations are indirectly addressed so the upper portion of RAM
can be used as stack space. Figure 3 shows the organization of
the internal Data Memory.
The first 32 bytes are reserved for four register banks of eight
bytes each. The processor uses one of the four banks as its
working registers depending on the RS1 and RS0 bits in the PSW
SFR. At reset, bank 0 is selected. If four register banks are not
required, use the unused banks as general purpose scratch pad
memory. The next 16 bytes (128 bits) are individually bit
addressable. The remaining bytes are byte addressable and can
be used as general purpose scratch pad memory. For addresses
0 - 7F
H
, use either direct or indirect addressing. For addresses
larger than 7F
H
, use only indirect addressing.
In addition to the internal Data Memory, the processor can access
64Kbytes of external Data Memory. The MOVX instruction
accesses external Data Memory.
2.1.2 Special Function Registers
Table 3 contains the SFR memory map. Unoccupied addresses
are not implemented on the device. Read accesses to these
addresses will return unknown values and write accesses will
have no effect.
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