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參數(shù)資料
| 型號(hào)： | 5962F9855202VXC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144 |
| 封裝： | CERAMIC, PGA-144 |
| 文件頁數(shù)： | 62/64頁 |
| 文件大小： | 1464K |
| 代理商： | 5962F9855202VXC |
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7
Bit Number
Mnemonic
Description
Bit 15
C
Carry. This conditional status is set if a carry is generated
or no borrow. [0]
Carry Equations:
C=
(Dm * Sm * Rm) + (Dm * Sm * Rm)
+(Dm * Sm * Rm)
Where: Dm destination register most significant bit
Sm - source register most significant bit
Rm - result most significant bit (stored in
destination register)
Bit 14
P
Positive. This conditional status is set if the result of an
operation is positive. [0]
Positive Equation: P = N * Z
Bit 13
Z
Zero. This conditional status is set if the result of an
operation is negative. [0]
Zero Equation:Z = Rm * Rm-1 * Rm-2 * R0
Bit 12
N
Negative. This conditional status is set if the result of an
operation is negative. [0]
Negative Equation: N = Rm
Bit 11
V
Overflow. This conditional status is set if the result when an
overflow condition occurs. [0]
Overflow Equation:
V = (Dm * Sm * Rm) + (Dm * Sm * Rm)
Bit 10
J
Normalized. This conditional status is set as the result of a
long instruction and the result is normalized. [0]
Normalized Equation: J = (R32 XOR R31)
Bit 9
IE
Interrupts Enabled. This bit reflects whether interrupts are
disabled or enabled. OTR Rd, ENBL and OTR Rd, DSBL
control this bit and function. [0]
Bit 8
MME
Discrete Input 1. This bit reflects the input stimulus applied
to the input pin.
Bit 7
RE
Receiver Error. This bit is the logical OR combination of the
OE, FE, and PE status bits. [0]
Bit 6
OE
Overrun Error. When active, this bit indicates that at least
one data word was lost because the Data Ready (DR bit 0 of
the Status Register) signal was active twice consecutively
without an INR Rd, RCVR. [0]
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