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參數(shù)資料
| 型號： | 5962F9855202QYC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CQFP132 |
| 封裝： | QFP-132 |
| 文件頁數(shù)： | 13/64頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | 5962F9855202QYC |
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20
Four signals make up the arbitration control bus -- Bus Request
(BRQ), Bus Grant (BGNT), Bus Busy (BUSY), and Bus Grant
Acknowledge (BGACK) .
4.1 Operand Bus Cycle Operation
The timing diagrams in figures 20, 21, and 22 show signal
relationships for the UT69R000 during an operand bus cycle
operation. The UT69R000 performs one of four operations
involving bus cycles on the Operand buses: (1) Memory Read,
(2) Memory Write, (3) I/O Read, and (4) I/O Write. The
UT69R000 performs all four bus cycle operations similarly.
The M/IO and R/WR signals determine the precise type of bus
cycle operation. For the following discussion, refer to figures
20, 21, and 22.
When the Operand bus arbitration process is complete and the
UT69R000 controls the Operand address and data buses, time
period CK3 begins. The UT69R000 signal controls the
Operand port at the beginning of time period CK3 by asserting
BGACK. STATE1 transitions from low to high. At the same
time, the following signals become valid: R/WR, M/IO, and
the Operand Address bus RA(15:0). Control signals R/WR and
M/IO determine the direction and type of bus cycle
taking place.
One-half clock cycle after the beginning of time period CK4
or one full clock cycle after the start of time period CK3, DS
goes active low. After DS has asserted, the UT69R000 samples
the DTACK input on every subsequent rising edge of OSCIN
to determine the duration of CK4. A bus cycle terminates one-
half clock cycle after the rising edge of OSCIN when the
UT69R000 detects assertion of DTACK. At this time, the
Operand Address Bus A (15:0) and the Operand bus control
signals (R/WR, M/IO) select the memory or I/O location from
which the Operand Data is read, or to which the Operand Data
is written. The UT69R000 also samples the
and
BTERR inputs on the same rising edge of OSCIN. These two
inputs indicate an error condition and terminate the current
bus cycle.
Figure 18. STRI Instruction Typical Timing
NEXT
DATA VALID (RSn)
STRI
NEXT ADDRESS
ADDRESS VALID (ACC)
DATA
RISC
ADDRESS
RISC
OSCIN
CK1
CK2
CK3
CK4
INSTRUCTION
STATE1
OE
WE
MPROT
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