- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360273 > 5962F9582201VXC Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs PDF資料下載
參數(shù)資料
| 型號： | 5962F9582201VXC |
| 英文描述： | Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs |
| 中文描述： | x1的SRAM |
| 文件頁數(shù)： | 37/41頁 |
| 文件大小： | 290K |
| 代理商： | 5962F9582201VXC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁第41頁
SIZE
A
5962-94663
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
B
SHEET
37
DSCC FORM 2234
APR 97
TABLE III. Pin descriptions - Continued.
Name
Type 1/
Active 2/
Description
Control signals
RD/
WR
TI
--
Read/Write. This indicates the direction of data flow with respect to the host. A
logic high signal means the host is trying to read data from the device, and a logic
low signal means the host is trying to write data to the device.
CS
TI
AL
Chip Select. This pin selects the device when accessing the internal registers.
RRD
TTO
AL
RAM Read. This signal is generated by the device to read data from RAM.
RWR
TTO
AL
RAM Write. This signal is generated by the device to write data to RAM.
RCS
TTO
AL
RAM Chip Select. This signal is used in conjunction with the
RRD
/
RWR
signal to
access RAM.
AUTOEN
TI
AL
Auto Enable. This pin, when active, enables automatic initialization.
ROMEN
TTO 3/
AL
ROM Enable. This pin, when active enables the ROM for automatic initialization
applications.
SSYSF
TI
AL
Subsystem Fail. Upon receipt, this signal propagates directly to the RT 1553 status
word.
24 MHz
CI
--
24 MHz Clock. This 24 MHz input clock requires a 50%
±
10% duty cycle with an
accuracy of
±
0.01%.
Master Reset. This input pin resets the internal encoders, decoders, all register,
and associated logic.
MRST
TUI
AL
MSEL1
TI
--
Mode Select 1. This pin is the most significant bit for the mode select. For proper
mode selection, see below:
MSEL1 MSEL0 Mode of Operation
0
0
0
1
1
0
1
1
Bus Controller = SBC
Remote Terminal = SRT
Monitor Terminal = SMT
SMT/SRT
MSEL0
TI
--
Mode Select 0. This pin is the least significant bit for the mode select. (See
MSEL1 for proper logic states.)
TCLK
TI
--
Timer Clock. This internal timer is a 16-bit counter with a 64
μ
s resolution when
using the 24 MHz input clock. For different applications, the user may input a
clock (0-60 MHz) to establish the timer resolution. (Duty Cycle = 50%
±
10%).
Military Standard A or B. This pin defines whether the device will be used a
MIL-STD-1553A or 1553B mode of operation.
A/
B
STD
TI
--
LOCK
TI
AL
Lock. This pin, when set active, prevents software changes to both the RT
address, A/
B
STD, and mode select.
See footnotes at end of table.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5962F9671502VCC | Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs |
| 5962F9671502VXC | Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs |
| 5962F9671602VEC | Synchronous Up Counter |
| 5962F9671602VXC | Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs |
| 5962F9671702VRC | Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962F9666301QXC | 制造商:Intersil Corporation 功能描述: |
| 5962F9666302QXC | 制造商:Intersil Corporation 功能描述: |
| 5962F9666302VXC | 制造商:Intersil Corporation 功能描述: |
| 5962F9669601VYC | 制造商:Harris Corporation 功能描述: |
| 5962F9671802VXC | 制造商:INTRSL 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。