參數(shù)資料
型號(hào)： 5962F9566101VRC
英文描述： 2-Wire, Serial, 8-Bit DACs with Rail-to-Rail Outputs
中文描述： 8位D型鎖存器
文件頁(yè)數(shù)： 15/41頁(yè)
文件大?。?/td> 290K
代理商： 5962F9566101VRC
SIZE
A
5962-94663
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
D
SHEET
15
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Limits
Test
Symbol
Test conditions 1/
-55
°
C
≤
T
C
≤
+125
°
C
4.5 V
≤
V
DD
≤
5.5 V
unless otherwise specified
Device
type
Group A
subgroups
Min
Max
Unit
AC electrical characteristics - Continued
Zero crossing stability
t
TZCS
V
CC
= minimum, see figure 5
Input TXIN and
TXIN
should
create transmitter output zero
crossings at 500 ns, 1000 ns,
1500 ns, and 2000 ns. These
zero crossings should not
deviate more than
±
25 ns
All
9, 10, 11
-25
+25
ns
1/
Device type 04 supplied to this drawing will meet all levels M, D, P, L, R of irradiation. Device type 05 supplied to this
drawing will meet all levels M, D, P, L, R, F, G, and H of irradiation. However, these devices are only tested at the 'R' and
'H' level, respectively. Device type 10 supplied to this drawing will meet level R of irradiation and will only be tested at level
R. Device type 11 supplied to this drawing will meet levels R and F of irradiation and will only be tested at level supplied.
Pre and post irradiation values are identical unless otherwise specified in table IA. When performing post irradiation
electrical measurements for any RHA level, T
A
= +25
°
C. All testing to be performed using worst case test conditions
unless otherwise specified. GND may not vary from 0 V by more than
±
50 mV. Unless otherwise specified,
V
CC
= 5.0 V
±
5% for device type 02; V
CC
= 5.0 V
±
10% for device types 05, 08, and 11; V
CC
= 5.0 V +10%, -5% and
V
EE
= -12.0 V or -15.0 V
±
5% for device types 01, 03, 04, 06, 07, 09, and 10.
24 MHz input only.
The worst case test condition is when IOL and IOH = 4.0 mA.
Supplied as a design limit but not guaranteed or tested.
Not more than one output may be shorted at a time for maximum duration of one second.
For all pins except CHA,
CHA
, CHB,
CHB
.
All inputs tied to V
DD
.
Post irradiation limit is 1.0 mA. Device type 11 post irradiation limit is 1.0 mA level R of irradiation and 5.0 mA level F of
irradiation.
For device types 07, 08, and 09, this parameter is guaranteed, but not tested.
10/ Guaranteed by characterization but not tested.
11/ Read cycle followed by a read cycle - minimum 45 ns.
Read cycle followed by a write cycle - minimum 45 ns.
Write cycle followed by a read cycle - minimum 85 ns.
Write cycle followed by a write cycle - minimum 85 ns.
12/ Minimum pulse width from latter rising edge of RD/
WR
or
CS
to first falling edge.
13/ Pulse width duration is measured with respect to the device recognizing
DTACK
assertion.
14/ Pass/fail criteria per the test method described in MIL-STD-1553, appendix A. RT validation test plan, section 5.1.2.2,
common mode rejection.
15/ Test in accordance with the method described in MIL-STD-1553B output symmetry, section 4.5.2.1.1.4.
16/ Tested on deivce types 07, 08, and 09 only.
2/
3/
4/
5/
6/
7/
8/
9/
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