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參數(shù)資料
| 型號： | 5962F9563801QYC |
| 廠商： | Aeroflex Inc. |
| 英文描述： | Radiation-Hardened MicroController |
| 中文描述： | 抗輻射微控制器 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 347K |
| 代理商： | 5962F9563801QYC |
10
6.0 AC CHARACTERISTICS READ CYCLE (Post-Radiation)*
(V
DD
= 5.0V
±
10%; -55
°
C < T
C
< +125
°
C)
Note:
* Post-radiation performance guaranteed at 25
°
C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).
1. Guaranteed, but not tested.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
t
CLCL
Clock Period
50
ns
1/t
CLCL
Oscillator Frequency
20
MHz
t
LHLL
ALE Pulse Width
2 t
CLCL
-40
ns
t
AVLL
Address Valid to ALE Low
t
CLCL
-40
ns
t
LLAX1
Address Hold after ALE Low
t
CLCL
-30
ns
t
LLIV
ALE Low to Valid Instruction
4 t
CLCL
-100
ns
t
LLPL
ALE Low to PSEN Low
t
CLCL
-30
ns
t
PLPH
PSEN Pulse Width
3 t
CLCL
-45
ns
t
PLIV
PSEN Low to Valid Instruction In
3 t
CLCL
-105
ns
t
PXIX1
Input Instruction Hold after PSEN
0
ns
t
PXIZ1
Input Instruction Float after PSEN
t
CLCL
-25
ns
t
AVIV
Address to Valid Instruction In
5 t
CLCL
-105
ns
t
PLAZ1
PSEN Low to Address Float
10
ns
t
RLRH
RD Pulse Width
6 t
CLCL
-100
ns
t
WLWH
WR Pulse Width
6 t
CLCL
-100
ns
t
RLDV
RD Low to Valid Data In
5 t
CLCL
-165
ns
t
RHDX1
Data Hold After RD High
0
ns
t
RHDZ1
Data Float After RD High
2 t
CLCL
-60
ns
t
LLDV
ALE Low Valid Data In
8 t
CLCL
-150
ns
t
AVDV
Address to Valid Data In
9 t
CLCL
-165
ns
t
LLWL
ALE Low to RD or WR Low
3 t
CLCL
-50
3 t
CLCL
+50
ns
t
AVWL
Address Valid to WR Low
4 t
CLCL
-130
ns
t
QVWX
Data Valid Before WR High
t
CLCL
-33
ns
t
WHQX
Data Hold After WR High
t
CLCL
-33
ns
t
QVWH
Data Valid to WR High
7 t
CLCL
-150
ns
t
RLAZ1
RD Low to Address Float
0
ns
t
WHLH
RD or WR High to ALE High
t
CLCL
-40
t
CLCL
+40
ns
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