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參數資料
| 型號： | 5962F1023305VXC |
| 元件分類： | 多路復用及模擬開關 |
| 英文描述： | 16-CHANNEL, SGL ENDED MULTIPLEXER, CDFP28 |
| 封裝： | CERAMIC, DFP-28 |
| 文件頁數： | 5/23頁 |
| 文件大?。?/td> | 474K |
| 代理商： | 5962F1023305VXC |
13
TIMING CHARACTERISTICS (UT16MX112)1,2
(AVDD=5.0V + 0.5V; -55C < TC < +125C)
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
tPROP_S
Propagation delay of analog input
(S[x]) to analog output (COM).
RT = 50
CL = 50pF
25
ns
tPROP_D
Propagation delay of any changes
in the digital inputs (A[3:0], CS,
PLATCH, SS) affecting the analog
output (COM).
RT = 50
CL = 50pF
See Figures 7 & 12.
25
140
ns
tMUX
Mux decoding time
RT = 50
CL = 50pF
See Figures 7 & 12.
50
ns
tBBM
Break-Before-Make-Delay
RT = 50
CL = 50pF
See Figures 7 & 12.
15
90
ns
tPZLH
Output enable time from HiZ to
Low or High once RESET is
pulled low.
RT = 50
CL = 50pF
See Figures 7 & 12.
90
ns
tPLHZ
Output disable time from Low or
High to HiZ once RESET is pulled
high.
RT = 50
CL = 50pF
See Figures 7 & 12.
55
ns
fSCLK
SCLK frequency
See Figure 7.
2.0
MHz
tH
SCLK high time
See Figure 7.
190
ns
tL
SCLK low time
See Figure 7.
190
ns
tSSU
First SCLK setup time (for
shifting window)
See Figure 7.
5.0
ns
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