參數(shù)資料
型號(hào): 5962F0153702QXC
元件分類: 多路復(fù)用及模擬開關(guān)
英文描述: QUAD 2-CHANNEL, CROSS POINT SWITCH, DFP64
封裝: DFP-64
文件頁(yè)數(shù): 8/14頁(yè)
文件大小: 81K
代理商: 5962F0153702QXC
3
TRUTH TABLE
PIN DESCRIPTION
Figure 2. UT54LVDS228 Pinout
UT54LVDM228
Crosspoint
Switch
64
63
62
61
60
59
58
57
VDD
1
En1
2
3
4
5
6
7
8
VSS
9
10
11
12
13
14
15
16
VDD
In4+
In4-
CLK In+
17
18
19
20
21
22
23
24
VSS
In5+
In6+
In6-
Sel1
Out2+
56
55
54
53
52
51
50
49
Out4+
CLK Out+
Out3-
Sel4
48
47
46
45
44
43
42
41
Out6-
CLK Out-
Out5-
In1+
En2
In2+
In3+
In3-
En3
En4
ENCK
CLK In-
En5
In5-
En6
Out1+
Out1-
Sel2
Out2-
VSS
Sel3
Out3+
Out4-
VDD
Out5+
VSS
Sel5
Sel6
Out6+
In7+
In7-
VDD
VSS
In8-
En8
En7
In8+
Out7+
VDD
VSS
Sel7
Out8-
Out7-
Sel8
Out8+
In1-
In2-
Out8-
Out5-
25
26
27
28
29
30
31
32
40
39
38
37
36
35
34
33
Sel1
Sel2
Out1
Out2
Mode
0
In1
1:2 splitter
0
1
In1
In2
Repeater
1
0
In2
In1
Switch
1
In2
1:2 splitter
Name
# of Pins
Description
In+
8
Non-inverting LVDS input
In-
8
Inverting LVDS input
Out+
8
Non-inverting LVDS output
Out-
8
Inverting LVDS Output
En
8
A logic low on the enable puts
the LVDS output into Tri-State
and reduces the supply current
ENCK
1
A logic low on the enable puts
the LVDS output into Tri-State
and reduces the supply current
Sel
8
2:1 mux input select
V
SS
6
Ground
VDD
5
Power supply
CLK In+
1
Non-Inverting Clock LVDS
Input
CLK In-
1
Inverting clock LVDS Input
CLK Out+
1
Non-Inverting Clock LVDS
Output
CLK Out-
1
Inverting Clock LVDS Output
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