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參數(shù)資料
| 型號： | 5962-9961601HXX |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | DUAL 3-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | GULLWING, CERAMIC, LCC-68 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 2449K |
| 代理商： | 5962-9961601HXX |
REV. 0
AD10465
–10–
AD10465 on any input by using the other inputs as alternate
locations for GND or an external resistor. The following chart
summarizes the impedance options available at each input
location:
AIN1 = 100
when A
IN2 and AIN3 are open.
AIN1 = 75
when AIN3 is shorted to GND.
AIN1 = 50
when AIN2 is shorted to GND.
AIN2 = 200
when A
IN3 is open.
AIN2 = 100
when AIN3 is shorted to GND.
AIN2 = 75
when AIN2 to AIN3 has an external resistor of
300
, with AIN3 shorted to GND.
AIN2 = 50
when AIN2 to AIN3 has an external resistor of
100
, with AIN3 shorted to GND.
AIN3 = 400
.
AIN3 = 100
when A
IN3 has an external resistor of 133
to
GND.
AIN3 = 75
when A
IN3 has an external resistor of 92
to
GND.
AIN3 = 50
when A
IN3 has an external resistor of 57
to
GND.
APPLYING THE AD10465
Encoding the AD10465
The AD10465 encode signal must be a high quality, extremely
low phase noise source, to prevent degradation of performance.
Maintaining 14-bit accuracy places a premium on encode clock
phase noise. SNR performance can easily degrade by 3 dB to
4 dB with 32 MHz input signals when using a high-jitter clock
source. See Analog Devices’ Application Note AN-501, “Aper-
ture Uncertainty and ADC System Performance” for complete
details. For optimum performance, the AD10465 must be clocked
differentially. The encode signal is usually ac-coupled into the
ENCODE and
ENCODE pins via a transformer or capacitors.
These pins are biased internally and require no additional bias.
Shown below is one preferred method for clocking the AD10465.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD10465 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to the other portions of the AD10465, and limits the
noise presented to the ENCODE inputs. A crystal clock oscillator
can also be used to drive the RF transformer if an appropriate
limiting resistor (typically 100
) is placed in the series with
the primary.
T1-4T
100
0.1nF
ENCODE
AD10465
HSMS2812
DIODES
CLOCK
SOURCE
Figure 6. Crystal Clock Oscillator, Differential Encode
If a low jitter ECL/PECL clock is available, another option is to
ac-couple a differential ECL/PECL signal to the encode input
pins as shown below. A device that offers excellent jitter perfor-
mance is the MC100LVEL16 (or same family) from Motorola.
ENCODE
AD10465
0.1 F
ECL/
PECL
VT
0.1 F
Figure 7. Differential ECL for Encode
Jitter Considerations
The signal-to-noise ratio (SNR) for an ADC can be predicted.
When normalized to ADC codes, Equation 1 accurately predicts
the SNR based on three terms. These are jitter, average DNL
error, and thermal noise. Each of these terms contributes to the
noise within the converter.
SNR
f
t rms
V
N
ANALOG
NOISE RMS
N
= ×
+
+
××
×
() +
20
1
2
12
log
/
ε
π
J
(1)
fANALOG
= analog input frequency.
tJ RMS
= rms jitter of the encode (rms sum of encode
source and internal encode circuitry).
ε
= average DNL of the ADC (typically 0.50 LSB).
N
= Number of bits in the ADC.
VNOISE RMS = V rms noise referred to the analog input of the
ADC (typically 5 LSB).
For a 14-bit analog-to-digital converter like the AD10465, aper-
ture jitter can greatly affect the SNR performance as the analog
frequency is increased. The chart below shows a family of curves
that demonstrates the expected SNR performance of the AD10465
as jitter increases. The chart is derived from the above equation.
For a complete discussion of aperture jitter, please consult
Analog Devices’ Application Note AN-501, “Aperture Uncer-
tainty and ADC System Performance.”
RMS CLOCK JITTER – ps
0.1
SNR
–
dBFS
60
AIN = 5MHz
AIN = 10MHz
AIN = 20MHz
AIN = 32MHz
0.3
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
0.7
1.1
1.5
1.9
2.3
2.7
3.1
3.5
3.9
61
62
63
64
65
66
67
68
69
70
71
Figure 8. SNR vs. Jitter
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