參數(shù)資料
型號(hào)： 5962-9853801Q2A
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC20
封裝： CERAMIC, LCC-20
文件頁數(shù)： 33/37頁
文件大?。?/td> 693K
代理商： 5962-9853801Q2A
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
I/O CLK
The I/O CLK can go up to 10 MHz for most of the voltage range when fast I/O is possible. The maximum I/O
CLK is limited to 2.8 MHz for a supply voltage range from 2.7 V. Table 1 lists the maximum I/O CLK frequencies
for all different supply voltage ranges. This also depends on input source impedance. For example, I/O CLK
speed faster than 2.39 MHz is achievable if the input source impedance is less than 1 k
.
Table 1. Maximum I/O CLK Frequency
VCC
MAXIMUM INPUT
RESISTANCE (Max)
SOURCE IMPEDANCE
I/O CLK
27 V
5K
1 k
2.39 MHz
2.7 V
5 K
100
2.81 MHz
45 V
1K
1 k
7.18 MHz
4.5 V
1 K
100
10 MHz
microprocessor serial interface
Input data bits from DATA IN are clocked in on the first four rising edges of the I/O CLK sequence if INV CLK
is held high when the device is in microprocessor interface mode. Input data bits are clocked in on the first four
falling edges of the I/O CLK sequence if INV CLK is held low. The MSB of the previous conversion appears on
DATA OUT on the falling edge of CS. The remaining nine bits are shifted out on the next nine edges (depending
on the state of INV CLK) of I/O CLK. Ten bits of data are transmitted to the host through DATA OUT.
A minimum of 9.5 clock pulses is required for the conversion to begin. On the tenth clock rising edge, the EOC
output goes low and returns to the high logic level when the conversion is complete; then the result can be read
by the host. On the tenth clock falling edge, the internal logic takes DATA OUT low to ensure that the remaining
bit values are zero if the I/O CLK transfer is more than ten clocks long.
CS is inactive (high) between serial I/O CLK transfers. Each transfer takes at least ten I/O CLK cycles. The falling
edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of
CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also,
the rising edge of CS disables I/O CLK and DATA IN within a setup time. A conversion does not begin until the
tenth I/O CLK rising edge.
A high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the output data register holds the previous conversion result). CS should not be taken
low close to completion of conversion because the output data can be corrupted.
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