
TLC7701, TLC7725, TLC7703, TLC7733, TLC7705
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087L DECEMBER 1994 REVISED FEBRUARY 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (see Note 2) (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TLC77xxM
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 2 V,
TA = 25°C
1.8
VDD = 2 V,
TA = 55°C to 125°C
1.7
IOH = 20 A
VDD = 2.7 V
TA = 25°C
2.5
VOH
High-level output
IOH = 20 A
VDD = 2.7 V
TA = 55°C to 125°C
2.3
V
VOH
High-level output
voltage
VDD = 4.5 V
TA = 25°C
4.3
V
voltage
VDD = 4.5 V
TA = 55°C to 125°C
4.2
IOH = 2 mA
VDD = 4.5 V
TA = 25°C
3.7
IOH = 2 mA
VDD = 4.5 V
TA = 55°C to 125°C
3.6
VDD = 2 V
TA = 25°C
0.2
VDD = 2 V
TA = 55°C to 125°C
0.2
IOL = 20 A
VDD = 2.7 V
TA = 25°C
0.2
VOL
Low-level output
IOL = 20 A
VDD = 2.7 V
TA = 55°C to 125°C
0.2
V
VOL
Low-level output
voltage
VDD = 4.5 V
TA = 25°C
0.2
V
voltage
VDD = 4.5 V
TA = 55°C to 125°C
0.2
IOL = 2 mA
VDD = 4.5 V
TA = 25°C
0.5
IOL = 2 mA
VDD = 4.5 V
TA = 55°C to 125°C
0.5
VIT
Negative-going input threshold
TLC7733
VDD = 2 V to 6 V
2.86
2.93
3.1
V
VIT
Negative-going input threshold
voltage, SENSE (see Note 3)
TLC7705
VDD = 2 V to 6 V
4.3
4.5
4.8
V
Vhys
Hysteresis voltage, SENSE
VDD = 2 V to 6 V
70
mV
Vres
Power-up reset voltage
IOL = 20 A
1
V
RESIN
VI = 0 V to VDD
2
II
Input current
CONTROL
VI = VDD
7
15
A
II
Input current
SENSE
VI = 5 V
5
10
A
SENSE, TLC7701 only
VI = 5 V
2
RESIN = VDD,
IDD
Supply current
RESIN = VDD,
SENSE = VDD ≥ VITmax + 0.2 V
CONTROL = 0 V,
Outputs open
916
A
IDD
Supply current
SENSE = VDD ≥ VITmax + 0.2 V
CONTROL = 0 V,
Outputs open
9
16
A
IDD(d) Supply current during td
TLC7733
VCT = 0 ,
RESIN = VDD,
CONTROL = 0 V,
VDD = 3.3 V
250
A
IDD(d) Supply current during td
TLC7705
DD
CONTROL = 0 V,
SENSE = VDD,
Outputs open
VDD = 5 V
120
150
A
CI
Input capacitance, SENSE
VI = 0 V to VDD
50
pF
Typical values apply at TA = 25°C.
The lowest supply voltage at which RESET becomes active. The symbol Vres is not currently listed within EIA or JEDEC standards for
semiconductor symbology. Rise time of VDD ≥ 15 s/V.
NOTES:
2. All characteristics are measured with CT = 0.1 F.
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1
F) should be placed near the supply terminals.