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參數(shù)資料
| 型號： | 5962-9566603Q2A |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 運算放大器 |
| 英文描述： | DUAL OP-AMP, 1000 uV OFFSET-MAX, 0.187 MHz BAND WIDTH, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數(shù)： | 32/61頁 |
| 文件大?。?/td> | 1557K |
| 代理商： | 5962-9566603Q2A |
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TLV225x, TLV225xA
Advanced LinCMOS RAILTORAIL
VERY LOW POWER OPERATIONAL AMPLIFIERS
SLOS185D FEBRUARY 1997 REVISED AUGUST 2006
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
driving large capacitive loads
The TLV2252 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 56
and Figure 57 illustrate its ability to drive loads up to 1000 pF while maintaining good gain and phase margins
(Rnull = 0).
A smaller series resistor (Rnull) at the output of the device (see Figure 60) improves the gain and phase margins
when driving large capacitive loads. Figure 55 and Figure 56 show the effects of adding series resistances of
10
, 50 , 100 , 200 , and 500 . The addition of this series resistor has two effects: the first adds a zero
to the transfer function and the second reduces the frequency of the pole associated with the output load in the
transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation 1 can be used.
φ
m1 + tan
–1 2 ×π × UGBW × R
null ×
C
L
φ
m1 + improvement in phase margin
UGBW
+ unity-gain bandwidth frequency
R
null + output series resistance
C
L + load capacitance
(1)
Where :
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 58). To
use equation 1, UGBW must be approximated from Figure 58.
Using equation 1 alone overestimates the improvement in phase margin as illustrated in Figure 59. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, providing
additional phase shift and reducing the overall improvement in phase margin.
Using Figure 60, with equation 1 enables the designer to choose the appropriate output series resistance to
optimize the design of circuits driving large capacitance loads.
50 k
50 k
VDD / GND
VDD +
Rnull
CL
VI
+
Figure 60. Series-Resistance Circuit
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相關代理商/技術參數(shù) |
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| 5962-9566701MEA | 功能描述:數(shù)模轉換器- DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| 5962-9571001MUA | 制造商:International Rectifier 功能描述:REG LDO LIN FIX NEG -12V 1.18A 3PIN TO-257AA ISOLATED - Rail/Tube |
| 5962-9571102MUA | 制造商:International Rectifier 功能描述:REG LDO LIN FIX NEG -5.2V 1.27A 3PIN TO-257AA ISOLATED - Rail/Tube |
| 59629571201Q3A | 制造商:TI 功能描述:SNJ54ABT843FK |
| 5962-9571201QLA | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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