參數(shù)資料
型號(hào)： 5962-9461107HMC
廠商： AUSTIN SEMICONDUCTOR INC
元件分類： SRAM
英文描述： 512K X 32 CACHE SRAM MODULE, 35 ns, CQFP68
封裝： CERAMIC, QFP-68
文件頁數(shù)： 11/12頁
文件大?。?/td> 223K
代理商： 5962-9461107HMC
SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
AS8S512K32 & AS8S512K32A
Rev. 3.0 6/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
7. At any given temperature and voltage condition,
t
HZCS, is less than tLZCS, and tHZWE is less than tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip selects and output
enable are held in their active state.
10. Address valid prior to or coincident with latest occurring
chip enable.
11. t
RC= READ cycle time.
12. Chip enable (CS\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
13. I
CC is for 32 bit mode.
NOTES
1. All voltages referenced to V
SS (GND).
2. -2V for pulse width <20ns.
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
4. This parameter guaranteed but not tested.
5. Test conditions as specified with output loading as
shown in Fig. 1 unless otherwise noted.
6. t
HZCS, tHZOE and tHZWE are specified with CL= 5pF as in Fig. 2.
Transition is measured +/- 200 mV typical from steady state
voltage, allowing for actual tester RC time constant.
RC(MIN)
unloaded, and f=
HZ.
t
1
LOW V
CC DATA RETENTION WAVEFORM
LOW POWER CHARACTERISTICS (L Version Only)