參數(shù)資料
型號: 5962-9458503H6X
元件分類: PROM
英文描述: 128K X 32 EEPROM 5V MODULE, 200 ns, CPGA66
封裝: CERAMIC, HIP-66
文件頁數(shù): 14/15頁
文件大?。?/td> 296K
代理商: 5962-9458503H6X
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WE128K32-XXX
PAGE WRITE OPERATION
The WE128K32-XXX has a page write operation that allows one to
128 bytes of data to be written into the device and consecutively
loads during the internal programming period. Successive bytes
may be loaded in the same manner after the first data byte has
been loaded. An internal timer begins a time out operation at each
write cycle. If another write cycle is completed within 150
s or
less, a new time out period begins. Each write cycle restarts the
delay period. The write cycles can be continued as long as the
interval is less than the time out period.
The usual procedure is to increment the least significant
address lines from A0 through A6 at each write cycle. In this
manner a page of up to 128 bytes can be loaded in to the
EEPROM in a burst mode before beginning the relatively long
interval programming cycle.
After the 150
s time out is completed, the EEPROM begins an
internal write cycle. During this cycle the entire page of bytes
will be written at the same time. The internal programming
cycle is the same regardless of the number of bytes accessed.
PAGE WRITE CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55
°C to +125°C)
FIG. 9
PAGE MODE
WRITE WAVEFORMS
1. Page address must remain valid for duration of write cycle.
Page Mode Write Characteristics
Symbol
Unit
Parameter
Min
Max
Write Cycle Time, TYP = 6ms
tWC
10
ms
Address Set-up Time
tAS
0ns
Address Hold Time (1)
tAH
100
ns
Data Set-up Time
tDS
100
ns
Data Hold Time
tDH
10
ns
Write Pulse Width
tWP
150
ns
Byte Load Cycle Time
tBLC
150
s
Write Pulse Width High
tWPH
50
ns
OE
BYTE 0
BYTE 1
BYTE 2
BYTE 3
VALID DATA
VALID
ADDRESS
t WC
t BLC
t WPH
t WP
ADDRESS
DATA
CS
WE
BYTE 127
t DS
t DH
t AS
t AH
x
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參數(shù)描述
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