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參數(shù)資料
| 型號(hào)： | 5962-9457501V2A |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 871K |
| 代理商： | 5962-9457501V2A |
UCC1806
UCC2806
UCC3806
SLUS272F -- FEBRUARY 2000 -- REVISED AUGUST 2006
6
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
PACKAGES
I/O
DESCRIPTION
NAME
D/DW/J/M
/N/PW
L,Q
I/O
DESCRIPTION
AOUT
11
14
O
High current gate drive for the external MOSFETs
BOUT
14
18
O
High-current gate drive for the external MOSFETs
COMP
7
9
O
Output of the error amplifier
CS--
3
4
I
Inverting input of the 3×, differential current sense amplifier
CS+
4
5
I
Non-inverting input of the 3×, differential current sense amplifier
CT
8
10
I
Oscillator timing capacitor connection point
CURLIM
1
2
I
Programs the primary current limit threshold that determins latching or retry after an
overcurrent situation
GND
12
15
--
Reference ground and power ground for all functions of this device
INV
6
8
I
Inverting input of the error amplifier.
NI
5
7
I
Non-nverting input of the error amplifier.
RT
9
12
I
Connection point for the oscillator timing resistor
SHUTDOWN
16
20
I
Provided for enhanced protection. When SHUTDOWN is driven above 1 V, AOUT and
BOUT are forced low.
SYNC
10
13
I/O
Allows providing external synchronization with TTL compatible thresholds.
VC
13
17
I
Input supply connection for the FET drive outputs.
VIN
15
19
I
Input supply connection for this device.
VREF
2
3
O
Reference output.
DETAILED PIN DESCRIPTIONS
AOUT and BOUT: AOUT and BOUT provide alternating high current gate drive for the external MOSFETs. Duty
cycle can be varied from 0% to 50% where minimum dead time is a function of CT. Both outputs use MOS
transistor switches with inherent anti-parallel body diodes to clamp voltage swings to the supply rails, allowing
operation without the use of clamp diodes.
COMP: COMP is the output of the error amplifier and the input of the PWM comparator. The error amplifier is
a low output impedance, 2-MHz operational amplifier which allows sinking or sourcing of current at the COMP
pin. The error amplifier is internally current limited, so that zero duty cycle can be commanded by externally
forcingCOMPtoGND.
CS--: CS-- is the inverting input of the 3× differential current sense amplifier.
CS+: CS+ is the non-inverting input of the 3× differential current sense amplifier.
CT: CT is the oscillator timing capacitor connection point, which is charged by the current set by RT. CT is
discharged to GND through a 2.5-mA current sink. This causes a linear discharge of CT to 0 V which then
initiates the next switching cycle. Dead time occurs during the discharge of CT, forcing AOUT and BOUT low.
Switching frequency (fS) and dead time (tD) are approximated by:
fS =
1
1.96 × RT × CT + tD
and tD = 956 × CT
(1)
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